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    METHOD FOR PRODUCING A LAYERED ASSEMBLY AND A LAYERED ASSEMBLY
    2.
    发明申请
    METHOD FOR PRODUCING A LAYERED ASSEMBLY AND A LAYERED ASSEMBLY 审中-公开
    一种用于生产层排列和层排列

    公开(公告)号：WO03050868A3

    公开(公告)日：2003-09-04

    申请号：PCT/DE0203998

    申请日：2002-10-23

    Applicant: INFINEON TECHNOLOGIES AG ,  KREUPL FRANZ ,  HOENLEIN WOLFGANG ,  STEINHOEGL WERNER

    Inventor： KREUPL FRANZ ,  HOENLEIN WOLFGANG ,  STEINHOEGL WERNER

    IPC: H01L21/768 ,  H01L51/30 ,  C01B31/02 ,  H01L23/522

    CPC classification number: H01L21/7682 ,  B82Y10/00 ,  H01L51/0048 ,  H01L2221/1047 ,  Y10S977/742

    Abstract: The invention relates to a method for producing a layered assembly and to a layered assembly (200). According to said method, two substantially parallel electrically conductive strip conductors (202, 203) are configured on a substrate and at least one auxiliary structure (205a, 205b, 205c) is configured on said substrate (201) between the two strip conductors (202, 203), running in a first direction (206), said first direction (206) forming an acute angle of at least 45 DEG or a right angle with a connecting axis of the strip conductors that runs at right angles to both strip conductors (202, 203). The invention is characterised in that the auxiliary structure or structures (205a, 205b, 205c) is or are produced from one material and said structure or structures can be selectively removed from the dielectric layer (204). In addition, a dielectric layer (204) is configured between the two strip conductors in such a way that the auxiliary structure or structures (205a, 205b, 205c) is or are at least partially covered by the dielectric layer (204).

    Abstract translation: 本发明涉及一种用于制造层结构的方法，和层布置。 在用于制造层结构（200），两个基本上相互平行的导电迹线（202,203）的方法形成在衬底上的衬底，至少一个辅助结构（205A，205B，205C）上（201） 且沿第一方向延伸的两个导体（202，203）之间（206）形成，该第一方向（206）与垂直于延伸的互连的连接轴线的锐角或直角两个互连（202，203）至少 包括45°的角度，其中，所述至少一个辅助结构（205A，205B，205C）由介电层（204）的至少一个辅助结构是可选择性去除的材料制成。 此外，在两个导体轨道之间形成的介电层（204），使得从电介质层（204）的所述至少一个辅助结构（205A，205B，205C）至少部分地被覆盖。

    SEMICONDUCTOR MEMORY WITH MEMORY CELLS COMPRISING A VERTICAL SELECTION TRANSISTOR AND METHOD FOR PRODUCTION THEREOF
    3.
    发明申请
    SEMICONDUCTOR MEMORY WITH MEMORY CELLS COMPRISING A VERTICAL SELECTION TRANSISTOR AND METHOD FOR PRODUCTION THEREOF 审中-公开
    包含垂直选择晶体管的具有存储器单元的半导体存储器及其制造方法

    公开(公告)号：WO03028104A3

    公开(公告)日：2003-08-14

    申请号：PCT/DE0202980

    申请日：2002-08-14

    Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

    Inventor： LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

    Abstract: A trench capacitor (30) is arranged in a first trench (25) for production of a semiconductor memory (5). A first longitudinal trench (55) is arranged in the substrate (15) next to the first trench (25) and parallel thereto on the other side of the first trench (25), a second longitudinal trench (60) is arranged therein. A first spacer word line (70) is arranged in the first longitudinal trench (55) and a second spacer word line (75) is arranged in the second longitudinal trench (60). Connecting webs (80) are arranged in the first trench (25) between the first spacer word line (70) and the second spacer word line (75) with a thickness (110), which is smaller in the direction of the first spacer word line (70) than half the width of the first trench (25) in the direction of the first spacer word line (70).

    Abstract translation: 为了制造半导体存储器（5），沟槽电容器（30）被布置在第一沟槽（25）中。 除了所述第一沟槽（25），第一纵向沟槽（55）和上第一沟槽并行（25），在所述基板的第二纵向沟槽（60）的另一侧（15）被布置。 在第一纵向沟槽（55）中设置第一间隔字线（70），在第二纵向沟槽（60）中设置第二间隔字线（75）。 在所述第一沟槽（25）的连接板（80）设置在所述第一间隔物的字线（70）和具有厚度（110）所述第二间隔的字线（75）（在第一间隔的字线70的方向之间 ）小于第一沟槽（25）朝向第一间隔字线（70）的宽度的一半。

    8.
    发明专利
    未知

    公开(公告)号：DE10131709A1

    公开(公告)日：2003-01-30

    申请号：DE10131709

    申请日：2001-06-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN

    IPC: H01L21/3213 ,  H01L21/8242

    Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.

    10.
    发明专利
    未知

    公开(公告)号：DE10131709B4

    公开(公告)日：2006-10-26

    申请号：DE10131709

    申请日：2001-06-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN

    IPC: H01L21/8242 ,  H01L21/3213

    Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.

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