公开(公告)号：DE10110626B4

公开(公告)日：2004-09-16

申请号：DE10110626

申请日：2001-03-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAFFROTH THILO ,  SCHNEIDER RALF

IPC: G01R21/10 ,  G01R31/28 ,  G01R15/04 ,  G01R19/165 ,  G01R31/26 ,  G11C29/00

公开(公告)号：DE10039350A1

公开(公告)日：2002-02-28

申请号：DE10039350

申请日：2000-08-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  WIRTH NORBERT ,  GRUBER ARNDT ,  RUF BERNHARD

IPC: G01R31/3177 ,  G11C7/00 ,  G11C29/00 ,  H01L21/66 ,  H01L31/0328

Abstract: An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

公开(公告)号：DE10259054B4

公开(公告)日：2006-10-26

申请号：DE10259054

申请日：2002-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  SCHROEDER STEPHAN ,  PROELL MANFRED ,  VOLLRATH JOERG

IPC: G05F1/46 ,  G05F3/30 ,  G11C11/4074 ,  G11C16/30 ,  H02M3/07

Abstract: A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit is downstream from an impedance converter and downstream a voltage generator. The bandgap reference circuit and the impedance converter on the one hand and the voltage generator on the other hand are connected to different reference ground potential line. The impedance converter contains a charge pump circuit to provide increased control potential, which drives the voltage generator. The voltage generator in contrast produces a reduced output potential. The influence of any voltage drop on that reference ground potential line to which the voltage generator is connected in the output potential is thus likewise reduced.

公开(公告)号：DE102004012629A1

公开(公告)日：2005-10-13

申请号：DE102004012629

申请日：2004-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOLLRATH JOERG ,  GNAT MARCIN ,  SCHNEIDER RALF ,  SCHROEDER STEFAN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/105 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/745 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

Abstract: A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.

公开(公告)号：DE10316579B4

公开(公告)日：2005-04-28

申请号：DE10316579

申请日：2003-04-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GNAT MARCIN ,  SCHNEIDER RALF ,  VOLLRATH JOERG

IPC: G11C7/10 ,  H03K19/00 ,  H03K19/0175

公开(公告)号：DE10316581A1

公开(公告)日：2004-11-04

申请号：DE10316581

申请日：2003-04-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOLLRATH JOERG ,  GNAT MARCIN ,  SCHNEIDER RALF

IPC: G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/08

Abstract: An integrated memory contains a memory cell array, which has word lines and bit lines, and a read/write amplifier, which is connected to the bit lines for the assessing and amplifying data signals. A voltage generator circuit generates a voltage supply for application to the read/write amplifier. A potential difference is applied to the read/write amplifier using different supply potentials. The voltage generator circuit increases the potential difference applied to the read/write amplifier for a limited period of time during an assessment and amplification operation of the read/write amplifier. Charge-dependent control is implemented in the voltage generator circuit. An assessment and amplification operation can be carried out at a comparatively high switching speed and a low power consumption is possible.

公开(公告)号：DE10260647B3

公开(公告)日：2004-08-26

申请号：DE10260647

申请日：2002-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  SCHROEDER STEPHAN ,  SCHNEIDER RALF ,  KLIEWER JOERG

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/407 ,  G11C7/12

Abstract: The DRAM (Dynamic Random Access Memory) includes a set of primary transmission amplifiers (SA) with bit conductors (BL), each connected to a cell block. Each cell block has a CSL (column select line) transistor (CSL1-3) with a common local data line (LDQ). Switches (MDQ/LDQ) connect a main data line (MDQ) to the local data line.

公开(公告)号：DE10258168A1

公开(公告)日：2004-07-08

申请号：DE10258168

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  SCHROEDER STEPHAN ,  SCHNEIDER RALF ,  KLIEWER JOERG

IPC: G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/12

Abstract: Local data lines (LDQT,LDQC) segmented as a column (Y) can each be linked in read/write cycles by a column-select line (CSL) switch (3) to primary sense amplifiers for delivering widened data signals to and from bit lines (BLT,BLC) in each segment (I,II,III). The CSL switch points to a column select signal supplied over a CSL running in a line direction (X). An Independent claim is also included for a method for operating an integrated semiconductor memory acting as dynamic random access memory (DRAM).

公开(公告)号：DE10124742C1

公开(公告)日：2003-01-23

申请号：DE10124742

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BUCKSCH THORSTEN ,  SCHNEIDER RALF

IPC: G11C29/34 ,  G11C29/00

Abstract: A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the target cell and neighboring cells which contain at least those cells for which is cannot be ruled out that their operation causes a fault-producing interaction. A data item is written to the target cell in order to produce one of two defined states. A write signal is applied to the neighboring cells in order to produce an undefined state which lies between the two defined states. The target cell and the neighboring cells are then read and the result of the reading process is used to check whether there is any interaction between the operation of the target cell and the operation of the neighboring cells.

公开(公告)号：DE59805775D1

公开(公告)日：2002-11-07

申请号：DE59805775

申请日：1998-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOHNSON BRET ,  SCHNEIDER RALF

IPC: H03K3/037 ,  H03K3/356

Abstract: The RS-flip-flop has an inverter (14) coupled to an input terminal (IN), a NOR gate (15) with an enable-set terminal (ENS) and a NAND gate (17) with an enable-reset terminal (ENR), each having a transistor (12,13) coupling it to the inverter. The outputs of the gates are coupled via the gate paths of the latter transistors to further transistors (16,18) with a common terminal coupled to the output of the inverter and providing the flip-flop output terminal (Q).