公开(公告)号：DE19933539B4

公开(公告)日：2005-08-04

申请号：DE19933539

申请日：1999-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  PARTSCH TORSTEN ,  DIETRICH STEFAN ,  WEIS CHRISTIAN

IPC: G11C7/10 ,  G11C11/407 ,  G11C11/4093

Abstract: A memory has an input circuit, which is provided adjacent to two groups of memory cells and via which two global data lines are connected to two local data lines. The memory has two operating states during which it feeds the data provided on the global data lines in respective different assignments to the two local data lines.

公开(公告)号：DE10208716A1

公开(公告)日：2003-09-18

申请号：DE10208716

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  ACHARYA PRAMOD ,  WEIS CHRISTIAN

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/407

公开(公告)号：DE10110624A1

公开(公告)日：2002-09-19

申请号：DE10110624

申请日：2001-03-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

IPC: G11C8/12

Abstract: The two memory regions (1,2) can be written with a datum at a preset address via a coupled data bus (11,12). The datum is applicable to the data bus via a data input circuit (10). Between the data bus and the two memory regions is incorporated a selector (14,15) each.According to the applied address, the selector supplies the datum to the first (1) or second memory region (2). The selector contains two circuits respectively allocated to one memory region. Independent claims are included for an integrated circuit used.

公开(公告)号：DE10053425A1

公开(公告)日：2002-05-29

申请号：DE10053425

申请日：2000-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARX THILO ,  HEYNE PATRICK ,  PARTSCH TORSTEN ,  HEIN THOMAS ,  SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  SOMMER MICHAEL

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00 ,  G11C11/407

公开(公告)号：DE10004110A1

公开(公告)日：2001-08-09

申请号：DE10004110

申请日：2000-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENINGER SABINE ,  WEIS CHRISTIAN

IPC: G11C7/10 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/409

Abstract: The method involves autoprecharging signal paths separately during the reading and the writing processes of memory. The internal running times of the autoprecharge process are different for the reading and the writing processes providing the autoprecharge to the memory cells as soon as possible when reading. An independent claim is also included for circuit arrangement for read/write control of memory.

公开(公告)号：DE50114518D1

公开(公告)日：2009-01-08

申请号：DE50114518

申请日：2001-10-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN DR ,  HEIN THOMAS ,  HEYNE PATRICK ,  MARX THILO ,  PARTSCH TORSTEN ,  SCHOENIGER SABINE ,  SCHROEGMEIER PETER ,  SOMMER MICHAEL ,  WEIS CHRISTIAN

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/18

公开(公告)号：DE102005046134A1

公开(公告)日：2007-04-12

申请号：DE102005046134

申请日：2005-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEIS CHRISTIAN ,  KALMS SVEN

IPC: H01L23/58 ,  G11C5/06 ,  H01L23/50

Abstract: Electronic component group (10) comprises electronic components (1-4) connected in series so that a number of input connections (11) of one component is connected to a number of output connections (12) of another component. The input connections and the output connections are arranged in the same geometric arrangement. An independent claim is also included for a method for transmitting information in electronic components. Preferred Features: Each electronic component is a rank of a digital memory. The geometric is mirror-symmetrical and/or rotation-symmetrical.

公开(公告)号：DE102005036528A1

公开(公告)日：2007-02-01

申请号：DE102005036528

申请日：2005-08-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  PLAETTNER ECKEHARD ,  WEIS CHRISTIAN

IPC: G11C7/10 ,  G11C11/4093

Abstract: The module has a scheduling circuit connected with a connection (4) for scheduling a connection with an adjustable resistance value. A control connection receives a control command signal. A control circuit (8) is connected with the scheduling circuit (5) to adjust the resistance value based on the control command signal and to schedule the connection. A control circuit is arranged in order to select one of the scheduling resistances. Independent claims are also included for the following: (1) a memory system with a memory controller (2) a method for operating a memory module.

公开(公告)号：DE102005019041A1

公开(公告)日：2006-11-02

申请号：DE102005019041

申请日：2005-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  PLAETTNER ECKEHARD ,  WEIS CHRISTIAN ,  JAKOBS ANDREAS

IPC: G11C7/22 ,  G11C11/4076

Abstract: The method involves transmitting a write instruction signal synchronized to a clock signal in memory circuits, and transmitting a write data signal that is synchronized to a strobe signal. A phase misalignment between the transmitted clock signal and the transmitted strobe signal is adjusted, and a write acceptance signal is generated depending on the clock signal and the write instruction signal with preset pulse duration. A number of edges of the strobe signals are determined, during the pulse duration. An independent claim is also included for a memory system with a memory circuit and a memory controller.

公开(公告)号：DE19925881B4

公开(公告)日：2005-08-11

申请号：DE19925881

申请日：1999-06-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

IPC: G11C7/10 ,  G11C11/4096 ,  G11C7/00 ,  G11C8/12