公开(公告)号：JP2004158860A

公开(公告)日：2004-06-03

申请号：JP2003375156

申请日：2003-11-05

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： MAZOYER PASCALE ,  VILLARET ALEXANDRE ,  SKOTNICKI THOMAS

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7888

Abstract: PROBLEM TO BE SOLVED: To realize a single transistor memory cell having the characteristics of a conventional SRAM and a flash memory. SOLUTION: In the memory circuit including at least one memory cell made of a single transistor, an insulating layer is formed between the gate and the channel regions of the transistor so that the insulating layer is parallel with each of the surfaces of the regions; a continuum of potential wells which are arranged with certain distances separated from the gate and the channel region, is formed in the insulating layer. Since the potential wells can include charges, two memory states concerning the memory cell state, i.e. "0"state, and "1" state can be defined by moving the charges to a first entrapping region direction next to the source region, or a second entrapping region direction next to the drain region. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2007258715A

公开(公告)日：2007-10-04

申请号：JP2007070062

申请日：2007-03-19

Applicant: St Microelectronics Sa ,  Stmicroelectronics (Crolles 2) Sas ,  エスティマイクロエレクトロニクス エスエー ,  エスティマイクロエレクトロニクス(クロル 2)エスエーエスSTMicroelectronics (Crolles 2)SAS

Inventor： MONFRAY STEPHANE ,  SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  TALBOT ALEXANDRE

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78684 ,  H01L29/66628 ,  H01L29/66772

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a transistor with a germanium-rich channel and fully-depleted type architecture that can be easily manufactured on an arbitrary substrate and that can easily control the formation of the channel.
SOLUTION: The manufacturing method for a MOS transistor comprises (a) a step to form a half-conductive interlayer 6 containing alloy of silicon and germanium on a substrate 2, (b) step to manufacture the source region, drain region and insulating gate regions 11, 12 and 9 of the transistor on the interlayer 6, and (c) step to oxidize the interlayer 6 starting with the bottom surface of the interlayer 6 to raise the concentration of germanium within the channel of the transistor.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有富锗的通道和全耗尽型结构的晶体管的制造方法，其可以容易地在任意的衬底上制造并且可以容易地控制通道的形成。 解决方案：MOS晶体管的制造方法包括（a）在衬底2上形成含有硅和锗的合金的半导体中间层6的步骤，（b）制造源极区，漏极区和 在中间层6上的晶体管的绝缘栅极区域11,12和9，以及（c）从中间层6的底面开始氧化中间层6的步骤，以提高锗在晶体管的沟道内的浓度。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003060095A

公开(公告)日：2003-02-28

申请号：JP2002178046

申请日：2002-06-19

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： SKOTNICKI THOMAS ,  VILLARET ALEXANDRE

IPC: H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/42336 ,  H01L29/788

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor memory device having hybrid performance. SOLUTION: The integrated semiconductor memory device is provided with an integrated memory structure CH2 provided with a semiconductor layer surrounded by an isolation layer, lying between the source region S and the drain region D of a transistor and inserted between the channel region of the transistor and its control gate. The semiconductor layer included two potential well zones Z1 and Z3 separated by a potential barrier zone Z2 lying beneath the control gate of the transistor. Write means Vg and Vds bias the memory structure so as to confine charge carriers selectively in one or other of the two potential well zones, and read means Vg and Vd bias the memory structure so as to detect, for example by measuring the drain current of the transistor, the presence of charge carriers in one or other of the potential wells.

Abstract translation: 要解决的问题：提供具有混合性能的集成半导体存储器件。 解决方案：集成半导体存储器件设置有集成存储器结构CH2，其设置有由隔离层围绕的半导体层，该隔离层位于晶体管的源极区域S和漏极区域D之间，并且插入在晶体管的沟道区域和晶体管的沟道区域之间 其控制门。 半导体层包括由位于晶体管的控制栅极下方的势垒区Z2分开的两个势阱区Z1和Z3。 写装置Vg和Vds偏置存储器结构，以便将电荷载流子选择性地限制在两个势阱区域中的一个或另一个中，并且读装置Vg和Vd偏置存储器结构，以便例如通过测量漏极电流 晶体管，在一个或另一个势阱中存在电荷载体。

公开(公告)号：WO0135448A2

公开(公告)日：2001-05-17

申请号：PCT/FR0003153

申请日：2000-11-10

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/60

Abstract: The invention concerns a method which consists in forming on a substrate (1) coated with a dielectric material layer (3) provided with a window (3a), a stack of successive layers alternately of germanium or SiGe alloy (4, 6, 8) and polycrystalline silicon (5, 7, 9); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material (10) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (11). The invention is useful for making dynamic random-access memories.

Abstract translation: 本发明涉及一种方法，该方法包括在涂覆有设置有窗口（3a）的介电材料层（3）的基底（1）上，交替地具有锗或SiGe合金（4,6,8）的叠层， 和多晶硅（5,7,9）; 选择性地部分消除锗或SiGe合金层，形成树状结构; 在树状结构上形成介电材料薄层（10）; 并用多晶硅（11）涂覆树状结构。 本发明对于制作动态随机存取存储器是有用的。

公开(公告)号：FR2865850B1

公开(公告)日：2006-08-04

申请号：FR0401018

申请日：2004-02-03

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  CHANEMOUGAME DANIEL ,  MONFRAY STEPHANE

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786

公开(公告)号：FR2844396A1

公开(公告)日：2004-03-12

申请号：FR0302772

申请日：2003-03-06

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： BUSTOS JESSY ,  CORONEL PHILIPPE ,  REGNIER CHRISTOPHE ,  WACQUANT FRANCOIS ,  TAVEL BRICE ,  SKOTNICKI THOMAS

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: The production of an electronic component consists of: (a) covering the surface (S) of a substrate (100) with a portion (P) delimiting with the substrate a volume (V) filled at least partially with a temporary material; (b) evacuating the temporary material from the volume by a shaft (C) extending between the volume and an access surface; (c) introducing an electrical conducting filling material (7) into the volume from some precursors fed via the shaft. Independent claims are also included for: (1) a field effect transistor with a gate produced by this method; (2) an electronic device incorporating such a transistor.

公开(公告)号：FR2818012B1

公开(公告)日：2003-02-21

申请号：FR0016174

申请日：2000-12-12

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  HAOND MICHEL

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/80 ,  H01L27/105

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

公开(公告)号：FR2823010A1

公开(公告)日：2002-10-04

申请号：FR0104437

申请日：2001-04-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JOSSE EMMANUEL

IPC: H01L21/336 ,  H01L29/165 ,  H01L29/78

Abstract: Production of a vertical transistor having an insulated gate with four-channel conduction comprises forming a vertical semiconductor column on a semiconductor substrate, and forming a dielectrically insulated semiconductor gate on the sides of the column and on the upper surface of the substrate. Formation of the column (PIL) comprises forming a first semiconductor column on the substrate, and forming a cavity in the primary column. Formation of the insulated gate comprises coating the internal walls of the cavity with a dielectric insulating material and filling the insulated cavity with gate material (14), so as to form, between the part of the insulated gate located in the cavity and the part of the insulated grid located on the sides of the column, two semiconductor connection regions (PL1, PL2) extending between the source and the drain of the transistor. An Independent claim is given for an integrated circuit comprising the vertical transistor.

公开(公告)号：FR2806833B1

公开(公告)日：2002-06-14

申请号：FR0003844

申请日：2000-03-27

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  HAOND MICHEL

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

公开(公告)号：FR2801970A1

公开(公告)日：2001-06-08

申请号：FR9915410

申请日：1999-12-07

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

IPC: G01D5/242 ,  G01L9/00 ,  G10K9/13 ,  G01D5/241 ,  H01L43/12

Abstract: The invention concerns a magnetic sensor comprising a thin deformable membrane (3) made of conductive material forming a first armature of a capacitor and traversed by an electric current, a second armature of a capacitor consisting of a doped zone of a semiconductor substrate (1), and a gaseous dielectric layer (6) separating the two armatures. The membrane is deformed under the effect of the Lorentz force generated by a magnetic field located in the plane of the membrane and perpendicular to the current lines. The invention also concerns a method for making said magnetic sensor and a device for measuring magnetic field.