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    46.
    发明专利
    未知

    公开(公告)号：DE60307475D1

    公开(公告)日：2006-09-21

    申请号：DE60307475

    申请日：2003-10-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SERGIO MAXIMILIAN ,  MANARESI NICOLO ,  TARTAGNI MARCO ,  GUERRIERI ROBERTO ,  CANEGALLO ROBERTO

    IPC: G01R27/02 ,  B60C23/06 ,  G01M17/02

    Abstract: The present invention refers to a method for the determination of the physical features of a tire, for example the deformations that it undergoes during the use.The method for the determination of the physical features of a tire, comprises at least a first belt (3,4) reinforced with a plurality of metallic wires, characterized by comprising the following phases: providing a signal between a first and a second metallic wire; determining the real part and the imaginary part of the impedance between said first metallic wire and said second metallic wire.

    48.
    发明专利
    未知

    公开(公告)号：DE69723814D1

    公开(公告)日：2003-09-04

    申请号：DE69723814

    申请日：1997-05-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PIERLUIGI ,  CANEGALLO ROBERTO ,  CHIOFFI ERNESTINA ,  GERNA DANILO ,  PASOTTI MARCO

    IPC: G11C27/00

    Abstract: For each cell (1) to be programmed, the present threshold value (Vo) of the cell is determined; the desired threshold value (VTAR) is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse (S) is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells (1) of a memory array (2) which is connected to a single word line (51) and to different bit lines (41 - 4N), each with a programming pulse (S1 - SN) the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.

    49.
    发明专利
    未知

    公开(公告)号：DE69628165D1

    公开(公告)日：2003-06-18

    申请号：DE69628165

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  LEONG PHILIP ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

    IPC: H03M1/74

    Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals and an output (OUT) for an analog signal, and comprising a current amplification circuit (AMP) having an input (ND) and an output coupled to the converter output; and a plurality of floating gate MOS transistors (M01, M11, M21, M31) corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference (GND) of potential, drain terminals coupled together and to the input (ND) of the amplification circuit (AMP), and control terminals coupleable, under control from the inputs of the plurality, to different references (GND,VCC) of potential having selected fixed values.

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