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48 records (took 0.022 seconds)

    41.
    发明专利
    未知

    公开(公告)号：DE60205909D1

    公开(公告)日：2005-10-06

    申请号：DE60205909

    申请日：2002-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  ZAMPROGNO MARCO ,  NAGARI ANGELO

    IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

    Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

    44.
    发明专利
    未知

    公开(公告)号：ITRM20010407D0

    公开(公告)日：2001-07-10

    申请号：ITRM20010407

    申请日：2001-07-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  ZAMPROGNO MARCO ,  NAGARI ANGELO

    IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

    Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

    45.
    发明专利
    未知

    公开(公告)号：DE69226021D1

    公开(公告)日：1998-07-30

    申请号：DE69226021

    申请日：1992-09-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CONFALONIERI PIERANGELO

    IPC: H03K17/06 ,  H03K17/687

    Abstract: A driver circuit for an electronic switch (2) which is to be operated from a clock signal (F) having a predetermined frequency, comprises an input pin (A) being applied the clock signal, and a voltage doubler (1) connected between said pin (A) and the switch (2).

    48.
    发明专利
    未知

    公开(公告)号：DE69707666D1

    公开(公告)日：2001-11-29

    申请号：DE69707666

    申请日：1997-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO

    IPC: H03M1/08 ,  H03H11/04 ,  H03H11/12 ,  H03H1/00

    Abstract: An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, comprising: a first resistor (R1) and a first capacitor (C1) which are parallel connected; an operational amplifier (3); a terminal of a second resistor (R2) which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor (R1) and the first capacitor (C1); a second capacitor (C2), which is fedback between the output of the operational amplifier and the inverting input; the filter further comprising an additional pair of resistors (R3A, R3B) which are arranged so as to be fedback between the output and the inverting input, a current signal (IDAC) arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.

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