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    44.
    发明专利
    未知

    公开(公告)号：DE69626972T2

    公开(公告)日：2004-01-08

    申请号：DE69626972

    申请日：1996-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FERRARI PAOLO ,  FORONI MARIO ,  VIGNA BENEDETTO ,  VILLA FLAVIO

    IPC: G01P15/02 ,  B81B3/00 ,  B81C1/00 ,  G01P15/08 ,  G01P15/125 ,  H01L29/84 ,  G01P15/00

    Abstract: The acceleration sensor is formed in a monocrystalline silicon wafer (4) forming part of a dedicated SOI substrate (50) presenting a first (1) and second (4) monocrystalline silicon wafer separated by an insulating layer (2) having an air gap (3). A well (15) is formed in the second wafer (4), over the air gap (3), and is subsequently trenched up to the air gap to release the monocrystalline silicon mass (23) forming the movable mass (24) of the sensor; the movable mass (24) has two numbers of movable electrodes (28a, 28b) facing respective pluralities of fixed electrodes (29a, 29b). In the idle condition, each movable electrode (28) is separated by different distances from the two fixed electrodes (29) facing the movable electrode.

    45.
    发明专利
    未知

    公开(公告)号：DE69528958T2

    公开(公告)日：2003-09-11

    申请号：DE69528958

    申请日：1995-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  FERRARI PAOLO

    IPC: H01L21/8222 ,  H01L27/06 ,  H01L29/861 ,  H01L27/00 ,  H01L27/02

    Abstract: A monolithic output stage which is self-protected against the occurrence of incidental latch-up phenomena and integrated in a portion of a semiconductor material chip which is isolated by a peripheral barrier structure linked electrically to a terminal (Vcc), specifically a supply terminal being applied thereto a constant voltage (+Vcc), has the barrier structure coupled to the terminal (Vcc) through a forward biased diode (D1) from the terminal (Vcc). The integrated barrier structure is formed within a region (21'') having a first type of conductivity, and comprises a heavily doped well (29) having the first type of conductivity and a substantially annular shape and contacting a large surface of the chip (22). This structure is characterized in that, in at least one portion thereof close to contact regions (S) for connection to said terminal (Vcc), the barrier well (29) is split into first and second heavily doped concentrical regions (29' and 29'') having the first type of conductivity. The barrier structure further comprises, located at said portion, an intermediate region (30) which is less heavily doped and also has the first type of conductivity, and a surface region (31) with a second type of conductivity located within said intermediate region. The invention preferably involves a power output stage including a vertical PNP transistor isolated by said barrier well.

    46.
    发明专利
    未知

    公开(公告)号：DE69717094T2

    公开(公告)日：2003-08-21

    申请号：DE69717094

    申请日：1997-07-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MURARI BRUNO ,  VIGNA BENEDETTO ,  FERRARI PAOLO

    IPC: G11B5/127 ,  G11B5/265 ,  G11B5/29 ,  G11B5/31 ,  G11B5/39 ,  G11B5/48 ,  G11B5/55 ,  G11B5/33 ,  G11B5/596

    Abstract: A head (130) for a disk storage device having a plurality of tracks (117) divided into memory cells (234) comprises means (205, 230a, 230b, 250a, 250b) for reading the memory cells (234) in succession, the means (205, 230a, 230b, 250a, 250b) for reading the memory cells (234) including at least two partial reading means (206a, 230a, 250a; 206b, 230b, 250b) each for reading a portion (234a; 234b) of each memory cell (234), the portions (234a; 234b) being arranged transversely relative to the longitudinal axis (233) of the corresponding track (117).

    47.
    发明专利
    未知

    公开(公告)号：DE69717094D1

    公开(公告)日：2002-12-19

    申请号：DE69717094

    申请日：1997-07-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MURARI BRUNO ,  VIGNA BENEDETTO ,  FERRARI PAOLO

    IPC: G11B5/127 ,  G11B5/265 ,  G11B5/29 ,  G11B5/31 ,  G11B5/39 ,  G11B5/48 ,  G11B5/55 ,  G11B5/33 ,  G11B5/596

    Abstract: A head (130) for a disk storage device having a plurality of tracks (117) divided into memory cells (234) comprises means (205, 230a, 230b, 250a, 250b) for reading the memory cells (234) in succession, the means (205, 230a, 230b, 250a, 250b) for reading the memory cells (234) including at least two partial reading means (206a, 230a, 250a; 206b, 230b, 250b) each for reading a portion (234a; 234b) of each memory cell (234), the portions (234a; 234b) being arranged transversely relative to the longitudinal axis (233) of the corresponding track (117).

    48.
    发明专利
    未知

    公开(公告)号：DE69617674D1

    公开(公告)日：2002-01-17

    申请号：DE69617674

    申请日：1996-09-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIGNA BENEDETTO ,  FERRARI PAOLO ,  MASTROMATTEO UBALDO

    IPC: G01P15/125 ,  B81B3/00 ,  B81C1/00 ,  G01P15/11 ,  H01L29/84 ,  G01P1/00

    Abstract: An acceleration sensor is described which is formed by planar technology on a substrate (10). It includes a core (11) of ferromagnetic material and, coupled conductively together by the core, a first winding (13) adapted to be connected to a power supply (14) and a second winding (15) adapted to be connected to circuit means (16) for measuring an electrical magnitude induced therein. The core (11) has two suspended portions which are free to bend as a result of an inertial force due to an accelerative movement of the sensor itself. The bending causes lengthening of the core (11) and hence a variation in the reluctance of the magnetic circuit. If a constant current is supplied to the first winding (13), a voltage is induced in the second winding (15) as a result of the variation in the magnetic flux caused by the variation in reluctance.

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