公开(公告)号：EP1408550A1

公开(公告)日：2004-04-14

申请号：EP02425605.9

申请日：2002-10-08

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Pellizzer, Fabio ,  Casagrande, Giulio ,  Bez, Roberto

IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

Abstract: A cell array (1) is formed by a plurality of cells (2) including each a selection bipolar transistor (4) and a storage component (3). The cell array is formed in a body (10) including a common collector region (11) of P type; a plurality of base regions (12) of N type, overlying the common collector region (11); a plurality of emitter regions (14) of P type formed in the base regions; and a plurality of base contact regions (15) of N type and a higher doping level than the base regions, formed in the base regions (12; 42), wherein each base region (12) is shared by at least two adjacent bipolar transistors (20).

Abstract translation: 电池阵列包括设置在主体（10）中的P型公共集电极区域（11）上的N型基极区域（12）的数量。 在基极区域中形成P型发射极区域（14）和N型基极接触区域（15），使得基极接触区域的掺杂水平高于基极区域的掺杂水平，并且每个基极区域由 至少两个双极晶体管（20）。 电池阵列制造过程中还包括独立权利要求。

公开(公告)号：EP1339110A9

公开(公告)日：2004-01-28

申请号：EP02425087.0

申请日：2002-02-20

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

公开(公告)号：EP1339111A1

公开(公告)日：2003-08-27

申请号：EP02425089.6

申请日：2002-02-20

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Pellizzer, Fabio

IPC: H01L45/00 ,  H01L27/24

CPC classification number: G11C11/5678 ,  G11C11/56 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y); and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) which is transverse to said first direction. The first and second thin portions (22, 38a) are in direct electrical contact and define a contact area (58) having sublithographic extent. The second thin portion (38a) is formed in a slit of sublithograhic dimensions. According to a first solution, oxide spacer portions (55a) are formed in a lithographic opening (51), delimited by a mold layer (49). According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

Abstract translation: 相变存储单元（5）由电阻元件（22）和相变材料的存储区域（38）形成。 电阻元件具有在第一方向（Y）上具有第一亚光刻尺寸的第一薄部分。 并且所述存储区域（38）具有在横向于所述第一方向的第二方向（X）上具有第二亚光刻尺寸的第二薄部分（38a）。 第一和第二薄部分（22,38a）处于直接电接触并且限定具有亚光刻范围的接触区域（58）。 第二薄部分（38a）形成在亚光刻尺寸的狭缝中。 根据第一解决方案，氧化物隔离部分（55a）形成在由模具层（49）限定的光刻开口（51）中。 根据不同的解决方案，牺牲区形成在模具层的顶部上，并用于在模具层中形成亚光刻缝。

公开(公告)号：EP1439579B1

公开(公告)日：2010-03-10

申请号：EP03425017.5

申请日：2003-01-15

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

IPC: H01L21/8238 ,  H01L27/24

CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

公开(公告)号：EP2045814A1

公开(公告)日：2009-04-08

申请号：EP07425616.5

申请日：2007-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio

IPC: G11C16/02 ,  G11C16/10 ,  G11C17/14 ,  G11C16/26

CPC classification number: G11C13/0069 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0078

Abstract: In a nonvolatile memory device, data stored in a memory cell (21a, 21b) are associated to whether or not the memory cell is switchable between a first state and a second state. Memory cells are irreversibly programmed by applying an irreversible programming signal (I IRP ), such that the nonvolatile memory cells (21a) are made not switchable between the first state and the second state in response to the irreversible programming signal (I IRP ). Reading memory cells includes: assessing (100, 110, 120, 140, 150, 160) whether a memory cell (21a, 21b) is switchable between a first state and a second state; determining that a first irreversible logic value ("1") is associated to the memory cell (21a), if the memory cell (21a) is not switchable between the first state and the second state (130); and determining that a second irreversible logic value ("0") is associated to the memory cell (21b), if the memory cell (21b) is switchable between the first state and the second state (170).

Abstract translation: 在非易失性存储器装置中，存储在存储器单元中的数据（21A，21B）被关联到所述存储器单元是否为第一状态和第二状态之间切换。 存储单元通过施加不可逆编程信号（I IRP）不可逆编程，检查做了非易失性存储单元（21a）的由响应于不可逆编程信号（I IRP）的第一状态和所述第二状态之间不切换。 读取存储器单元包括：评估（100，110，120，140，150，160）是否存储单元（21A，21B）为第一状态和第二状态之间切换; 确定性挖掘做了第一不可逆逻辑值（“1”）关联到所述存储单元（21a），如果存储单元（21a）没有所述第一状态和所述第二状态（130）之间切换; 和确定性挖掘做了第二不可逆逻辑值（“0”）被关联到所述存储单元（21B），如果存储单元（21B）是在第一状态和第二状态（170）之间切换。

公开(公告)号：EP1326254B1

公开(公告)日：2009-02-25

申请号：EP01830806.4

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Bosisio, Giorgio ,  Pellizzer, Fabio

IPC: G11C11/34

CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

公开(公告)号：EP1845567A1

公开(公告)日：2007-10-17

申请号：EP06425257.0

申请日：2006-04-11

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Ottogalli, Federica

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase-change memory cell (61), formed by a phase-change memory element (64) and by a selection element (65), which is formed in a semiconductor material body (20) and is connected to the phase-change memory element (64). The phase-change memory element (64) is made up of a chalcogenic material layer (17) and a heater (63). The selection element (65) is in direct contact with the heater (63) and extends through a dielectric region (38,24) arranged on top of and contiguous to the semiconductor material body (20). A dielectric material layer (32) is arranged on the dielectric region (24) and houses a portion of the chalcogenic material layer (17).

Abstract translation: 由相变存储元件（64）和选择元件（65）形成的相变存储单元（61），其形成在半导体材料体（20）中，并连接到相变存储元件 （64）。 相变存储元件（64）由硫属材料层（17）和加热器（63）构成。 选择元件（65）与加热器（63）直接接触并且延伸穿过布置在半导体材料体（20）顶部并邻近半导体材料体（20）的电介质区域（38,24）。 介电材料层（32）布置在电介质区域（24）上并容纳一部分硫属材料层（17）。

公开(公告)号：EP1489622B1

公开(公告)日：2007-08-15

申请号：EP03425390.6

申请日：2003-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Casagrande, Giulio

IPC: G11C11/34

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

公开(公告)号：EP1729355A1

公开(公告)日：2006-12-06

申请号：EP05104879.1

申请日：2005-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Varesi, Enrico ,  Pirovano, Agostino ,  Petruzza, Pietro

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.

Abstract translation: 用于制造相变存储单元的方法包括在半导体晶片（10）中形成加热元件（25a）和在与加热器元件（25a）接触并与之接触的相变材料的存储区域（31a）的步骤。 为了形成加热器元件（25a）和相变储存区域（31a），首先形成加热器结构，并且相变层（31）沉积在加热器结构上并与加热器结构接触。 然后，通过随后的自对准蚀刻步骤限定相变层（31）和加热器结构。

公开(公告)号：EP1675183A1

公开(公告)日：2006-06-28

申请号：EP04425931.5

申请日：2004-12-21

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Pirovano, Agostino

IPC: H01L27/24

CPC classification number: H01L27/2409 ,  G11C13/0016 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory cell (2) includes a memory element (3) and a selection element (30) coupled to said memory element (3). The selection element (30) includes a first junction portion (128a), having a first type of conductivity, and a second junction portion (128b), having a second type of conductivity and forming a rectifying junction (38) with the first junction portion (128a). The first junction portion (128a) and the second junction portion (128b) are made of materials selected in the group consisting of: chalcogenides and conducting polymers.

Abstract translation: 存储单元（2）包括存储元件（3）和耦合到所述存储元件（3）的选择元件（30）。 选择元件（30）包括具有第一类型导电性的第一接合部分（128a）和具有第二类型导电性的第二接合部分（128b），并且与第一接合部分形成整流接头（38） （128A）。 第一接合部分（128a）和第二接合部分（128b）由选自以下的材料制成：硫族化物和导电聚合物。