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41.发明申请公开(公告)号：US20120034822A1
公开(公告)日：2012-02-09
申请号：US12849593
申请日：2010-08-03
Applicant: STEVEN RICHARD BOPP , NEIL KTUL NAY
Inventor： STEVEN RICHARD BOPP , NEIL KTUL NAY
CPC classification number: H01R13/6466 , H01R13/6461 , H01R13/6469 , H01R24/64 , H01R2107/00 , H05K1/0228 , H05K1/0239 , H05K1/11 , H05K2201/07 , H05K2201/10189
Abstract: An electrical connector that includes a circuit board having a board substrate that has opposite board surfaces and a thickness measured along an orientation axis that extends between the opposite board surfaces. The circuit board has associated pairs of input and output terminals and signal traces that electrically connect the associated pairs of input and output terminals. The input and output terminals being configured to communicatively coupled to mating and cable conductors, respectively. Each associated pair of input and output terminals is electrically connected through a corresponding signal trace that has a conductive path extending along the board substrate between the corresponding input and output terminals. At least two signal traces form a broadside-coupling region in which the conductive paths of the at least two signal traces are stacked along the orientation axis and spaced apart through the thickness and extend parallel to each other for a crosstalk-reducing distance.
Abstract translation: 一种电连接器，包括具有板基板的电路板，该基板具有相对的板表面，并且沿着在相对的板表面之间延伸的取向轴线测量的厚度。 电路板具有相关联的输入和输出端子对以及电连接相关联的输入和输出端子对的信号迹线。 输入和输出端子分别被配置为可通信地耦合到配合电缆导体和电缆导体。 每个相关联的输入和输出端子对通过相应的信号迹线电连接，该对应的信号迹线具有沿对应的输入和输出端子之间的板基板延伸的导电路径。 至少两个信号迹线形成宽侧耦合区域，其中至少两个信号迹线的导电路径沿着取向轴线堆叠并且间隔开厚度并且彼此平行延伸以减少串扰减小距离。
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公开(公告)号：US10004137B2
公开(公告)日：2018-06-19
申请号：US15408672
申请日：2017-01-18
Applicant: Silicon Motion, Inc.
Inventor： I-Hung Huang
CPC classification number: H05K1/0271 , G01R1/0416 , G01R31/003 , G01R31/44 , H05K1/0298 , H05K1/111 , H05K1/115 , H05K1/18 , H05K3/28 , H05K2201/07 , H05K2201/09909 , H05K2201/09972
Abstract: The present invention provides a printed circuit board assembly including a substrate having a plurality of conductive layers vertically sandwiched between a first cap-insulation layer and a second cap-insulation layer. The substrate has a first part, a second part and a third part. For protecting the conductive layers from moisture, each of the areas of the conductive layers corresponding to the second part is smaller than the area of the first cap-insulation layer corresponding to the second part for at least a first predetermined percentage, and each of the areas of the conductive layers corresponding to the second part is smaller than the area of the second cap-insulation layer corresponding to the second part for at least the first predetermined percentage.
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43.发明申请公开(公告)号：US20180153026A1
公开(公告)日：2018-05-31
申请号：US15882256
申请日：2018-01-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Cheng
CPC classification number: H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
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公开(公告)号：US09986635B2
公开(公告)日：2018-05-29
申请号：US15379778
申请日：2016-12-15
Inventor： Wilhelm Neukam
CPC classification number: H05K1/0275 , H05K1/0284 , H05K1/03 , H05K3/20 , H05K5/0208 , H05K7/1427 , H05K2201/0388 , H05K2201/07 , H05K2201/09154 , H05K2201/09681
Abstract: An assembly includes a carrier and an electrically conductive mesh, wherein the carrier includes a side surface with an edge, the electrically conductive mesh is attached to the side surface and extends over the edge of the side surface, and the edge has a radius at least as big as a minimal bending radius of electric lines of the electrically conductive mesh.
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公开(公告)号：US09860986B2
公开(公告)日：2018-01-02
申请号：US15310530
申请日：2015-03-05
Applicant: Auto-Kabel Management GmbH
Inventor： Wacim Tazarine , Simon Betscher , Frank Gronwald , Sohejl Rafati
CPC classification number: H05K1/14 , F02N11/0862 , F02N11/087 , F02N2011/0874 , F02N2250/02 , H05K1/0204 , H05K1/0263 , H05K1/0287 , H05K1/056 , H05K1/09 , H05K1/111 , H05K1/142 , H05K1/145 , H05K2201/04 , H05K2201/06 , H05K2201/07 , H05K2201/10166 , H05K2201/10174 , H05K2201/10272
Abstract: Circuit arrangement for vehicles with at least one semiconductor element 30 and at least one first metal carrier plate 2a and a metal circuit board 2b. A multifaceted scope of application is provided if the carrier plate 2a is electrically insulated from the circuit board 2b and the carrier plate 2a is electrically linked with at least one of the circuit boards 2b by means of at least one semiconductor device 30 so that the carrier plate 2a and the circuit board 2b form an electrical three-pole.
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Patent Agency Ranking
公开(公告)号：US09730313B2
公开(公告)日：2017-08-08
申请号：US14947065
申请日：2015-11-20
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, Jr. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers; an antipad of a first type around and between the first and second signal vias in one or more of the attachment layers; and antipads of a second type around the first and second signal vias in at least one routing layer adjacent to the breakout layer.
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公开(公告)号：US20170171964A1
公开(公告)日：2017-06-15
申请号：US15271800
申请日：2016-09-21
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Brian M. Erwin
CPC classification number: H05K1/0275 , B05D3/102 , B41N1/083 , C23C22/66 , C23C22/76 , C23C22/78 , C25D11/04 , C25D11/045 , C25D11/16 , H01L23/57 , H05K1/00 , H05K1/0306 , H05K1/0393 , H05K1/09 , H05K1/115 , H05K1/16 , H05K3/06 , H05K3/28 , H05K3/4038 , H05K3/4602 , H05K3/4644 , H05K3/4682 , H05K3/4697 , H05K2201/07 , H05K2201/09681 , H05K2203/0307 , H05K2203/0315 , H05K2203/033 , H05K2203/0369 , H05K2203/0392 , H05K2203/0733 , H05K2203/1142
Abstract: A method of making a security mesh comprises forming on a conductive substrate an alumina film having through-holes in which metal, e.g., copper, through-wires are formed. First surface wires are formed on one surface of the alumina film and second surface wires are formed on the second, opposite surface of the alumina film in order to connect selected through-wires into a continuous undulating electrical circuit embedded within the alumina film. The security mesh product comprises an alumina film having a continuous undulating electrical circuit comprising copper or other conductive metal extending therethrough. A stacked security mesh comprises two or more of the mesh products being stacked one above the other.
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48.发明申请THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE 审中-公开三维集成电路静电放电保护和预防测试界面公开(公告)号：US20160113099A1
公开(公告)日：2016-04-21
申请号：US14975951
申请日：2015-12-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Mill-Jer WANG , Ching-Nen PENG , Hung-Chih LIN , Hao CHEN
CPC classification number: H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
Abstract translation: 本公开提供了一种用于提供静电放电保护的系统和方法。 提供一种电连接到多个输入/输出通道的探针卡组件。 探针卡组件可以与具有电连接到一个或多个晶片的插入器的次级组件接触，每个晶片具有被测器件。 可以将电压强制在探针卡组件的多个输入/输出通道中的一个上，以缓慢地耗散驻留在晶片上的电荷，从而提供静电放电保护。 还提供了适于接受3DIC封装的插座组件，该组件具有电连接到多个输入/输出通道的装载板组件。 一旦将3DIC封装放置在插座组件中，则强制在输入/输出通道之间施加电压以缓慢耗散驻留在3DIC封装上的电荷，从而提供静电放电保护。
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49.发明授权公开(公告)号：US09252593B2
公开(公告)日：2016-02-02
申请号：US13716272
申请日：2012-12-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
CPC classification number: H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
Abstract translation: 本公开提供了一种用于提供静电放电保护的系统和方法。 提供一种电连接到多个输入/输出通道的探针卡组件。 探针卡组件可以与具有电连接到一个或多个晶片的插入器的次级组件接触，每个晶片具有被测器件。 可以将电压强制在探针卡组件的多个输入/输出通道中的一个上，以缓慢地耗散驻留在晶片上的电荷，从而提供静电放电保护。 还提供了适于接受3DIC封装的插座组件，该组件具有电连接到多个输入/输出通道的装载板组件。 一旦将3DIC封装放置在插座组件中，则强制在输入/输出通道之间施加电压以缓慢耗散驻留在3DIC封装上的电荷，从而提供静电放电保护。
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50.发明申请公开(公告)号：US20140167799A1
公开(公告)日：2014-06-19
申请号：US13716272
申请日：2012-12-17
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Mill-Jer WANG , Ching-Nen PENG , Hung-Chih LIN , Hao CHEN
CPC classification number: H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
Abstract translation: 本公开提供了一种用于提供静电放电保护的系统和方法。 提供一种电连接到多个输入/输出通道的探针卡组件。 探针卡组件可以与具有电连接到一个或多个晶片的插入器的次级组件接触，每个晶片具有被测器件。 可以将电压强制在探针卡组件的多个输入/输出通道中的一个上，以缓慢地耗散驻留在晶片上的电荷，从而提供静电放电保护。 还提供了适于接受3DIC封装的插座组件，该组件具有电连接到多个输入/输出通道的装载板组件。 一旦将3DIC封装放置在插座组件中，则强制在输入/输出通道之间施加电压以缓慢耗散驻留在3DIC封装上的电荷，从而提供静电放电保护。
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