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公开(公告)号：JP2011040720A
公开(公告)日：2011-02-24
申请号：JP2010140852
申请日：2010-06-21
Applicant: Nan Ya Printed Circuit Board Corp , 南亞電路板股▲ふん▼有限公司
Inventor： LIN HSIEN-CHIEH
CPC classification number: H05K3/3457 , H05K1/116 , H05K3/3452 , H05K3/4092 , H05K3/4644 , H05K2201/0397 , H05K2201/092 , H05K2201/09436 , H05K2201/09781 , H05K2203/043
Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit board and a manufacturing method thereof. SOLUTION: The printed circuit board includes: a circuit board having an internal circuit structure; an additional circuit structure provided on the circuit board and electrically connected to the internal circuit structure; a solder resist insulation layer that is provided on the additional circuit structure and has an opening; a conductive bump pattern that is provided inside the solder resist insulation layer and has a portion extending in the horizontal direction of the opening to expose its one side, part of the top surface, and part of the bottom surface out of the opening; and a solder ball formed in the opening and electrically connected to the additional circuit structure. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：提供一种印刷电路板及其制造方法。 解决方案：印刷电路板包括：具有内部电路结构的电路板; 设置在电路板上并电连接到内部电路结构的附加电路结构; 阻焊绝缘层，设置在附加电路结构上并具有开口; 导电凸块图形，其设置在所述阻焊剂绝缘层的内部，并且具有在所述开口的水平方向上延伸的部分，以使其一侧，所述顶表面的一部分和所述底表面的一部分露出所述开口; 以及形成在开口中并电连接到附加电路结构的焊球。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP2008210974A
公开(公告)日：2008-09-11
申请号：JP2007045850
申请日：2007-02-26
Applicant: Hitachi Ltd , 株式会社日立製作所
Inventor： SUEYOSHI JUNYA
CPC classification number: H05K3/308 , H01R12/585 , H05K3/325 , H05K2201/092 , H05K2201/10189 , H05K2201/10303 , H05K2201/1059 , H05K2201/10878
Abstract: PROBLEM TO BE SOLVED: To suppress an electrostatic capacity of a through-hole of a high density/highly-multilayered printed-circuit board for transmitting a high-speed signal. SOLUTION: The through-hole for press fittig a press-fit pin is formed to the printed-circuit board of this invention. The printed-circuit board comprises at least one signal transmission layer, a wiring pattern for signal transmission formed to at least the one signal transmission layer, and an electrode part of the wiring pattern for signal transmission exposing on an inner circumferential surface of the through-hole. The electrode is formed not on the whole inner circumferential surface of the through-hole, but on only a part of it. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 解决的问题：抑制用于传输高速信号的高密度/高度多层印刷电路板的通孔的静电电容。 解决方案：本发明的印刷电路板形成有用于压入压配合销的通孔。 印刷电路板包括至少一个信号传输层，至少形成在一个信号传输层上的用于信号传输的布线图形，以及用于信号传输的布线图案的电极部分，其在通孔的内圆周表面上露出， 孔。 电极不形成在通孔的整个内周面上，而是仅形成在其一部分上。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：KR100393243B1
公开(公告)日：2003-07-31
申请号：KR1019997008216
申请日：1997-03-12
Applicant: 지멘스 악티엔게젤샤프트
Inventor： 부쉬,게오르크
IPC: H05K1/02
CPC classification number: H05K1/0224 , H05K1/0237 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K2201/0715 , H05K2201/092 , H05K2201/093 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/0969 , H05K2201/09845 , H05K2203/1438
Abstract: 본 발명은 HF 부품을 가지는 전기 장치, 특히 이동 무선통신 장비에 사용되는 회로 기판상의 전기 회로와 인쇄된 도체 구조의 팩킹 밀도를 증가시키는 것이다. 결국, "마이크로 비아" 층(M2)이 우선 회로 기판(LPT4)의 한쪽 또는 양쪽에 부가된다. 그후, 특히 HF 회로와 HF 인쇄된 도체 구조(LBS3HF)가 "마이크로 비아" 층(M2)상에 배치된다. 상기 HF 회로와 HF 인쇄된 도체 구조(LBS3HF)는 HF 회로 또는 HF 인쇄된 도체 구조(LBS3HF)의 조절될 수 있는 HF 파라미터에 영향을 끼치는 방해 간섭에 대해 "마이크로 비아" 층(M2) 아래에 직접 배치되는 회로 기판층의 기판층(LPL2)에 배열된 차단 영역에 의해 회로 기판의 HF 매스 층과 관련하여 보호된다.
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公开(公告)号：JP2011103441A
公开(公告)日：2011-05-26
申请号：JP2010190604
申请日：2010-08-27
Applicant: Fujitsu Ltd , 富士通株式会社
Inventor： MIZUTANI DAISUKE
CPC classification number: H05K1/147 , H01L21/76898 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H05K1/0218 , H05K1/141 , H05K3/222 , H05K3/3436 , H05K3/363 , H05K2201/0379 , H05K2201/0715 , H05K2201/09063 , H05K2201/092 , H05K2201/10666 , H05K2201/10734 , H05K2203/167 , Y02P70/613 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same, which facilitate alignment between a semiconductor component and a circuit board. SOLUTION: The semiconductor device includes a first circuit base member 20 including a surface having multiple first electrodes 22 formed thereon, a second circuit base member 30 being provided above the first circuit base member 20 and having first through-holes 30a and second through-holes 30b formed respectively above the first electrodes 22, a semiconductor package 50 provided above the second circuit base member 30, and multiple first bumps 51 provided inside the first through-holes 30a and the second through-holes 30b to connect the first electrodes 22 to the semiconductor package 50. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 解决的问题：提供一种半导体器件和电路板之间的对准的半导体器件及其制造方法。 解决方案：半导体器件包括第一电路基底构件20，其包括形成有多个第一电极22的表面，第二电路基底构件30设置在第一电路基底构件20的上方，并具有第一通孔30a和第二通孔30a 设置在第一电极22上方的通孔30b，设置在第二电路基体30上方的半导体封装50以及设置在第一通孔30a和第二通孔30b内部的多个第一凸起51，以将第一电极 （C）2011，JPO＆INPIT
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公开(公告)号：JP4611010B2
公开(公告)日：2011-01-12
申请号：JP2004359169
申请日：2004-12-10
Applicant: 日立ビアメカニクス株式会社
IPC: H05K3/46
CPC classification number: H05K3/429 , H05K1/0268 , H05K3/0047 , H05K2201/092 , H05K2201/09718 , H05K2201/09845 , H05K2203/0207 , H05K2203/0242 , H05K2203/163 , H05K2203/175 , Y10T428/24322 , Y10T428/24917 , Y10T428/24926
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Patent Agency Ranking
公开(公告)号：KR100273933B1
公开(公告)日：2000-12-15
申请号：KR1019950042210
申请日：1995-11-20
Applicant: 인터내셔널 비지네스 머신즈 코포레이션
Inventor： 아닐쿠마치누프라사드바트 , 로이하비매그너슨 , 보야리스타마르코비치 , 콘스탄티노스파파토마스 , 더글러스올리버파웰
IPC: H05K3/40
CPC classification number: H05K3/0094 , H01L23/5384 , H01L2224/16 , H01L2224/16225 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K1/112 , H05K3/0023 , H05K3/429 , H05K3/4602 , H05K2201/092 , H05K2201/09472 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09845 , H05K2201/10734 , H05K2203/0191 , H05K2203/0278 , Y10T29/49126 , Y10T29/49165
Abstract: 본 발명은 인쇄 회로 기판 및 인쇄 회로 기판을 제조하는 방법을 개시하고 있다. 인쇄 회로 기판은 두 가지 유형의 도금 스루 홀을 구비한다. 제1 유형의 도금 스루 홀은 핀-인-스루-홀(pin-in-through-hole) 모듈 또는 부품 핀을 수용하기 위하여 인쇄 회로 기판의 외부 표면으로 외부 표면을 관통하여 연장된다. 제2 유형의 도금 스루 홀은 표면 실장을 위한 것이고 인쇄 회로 기판의 외부 표면의 아래에서 종단된다. 이들 도금 스루 홀은 충전 조성물(fill composition)을 포함한다.
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公开(公告)号：US09030007B2
公开(公告)日：2015-05-12
申请号：US12903403
申请日：2010-10-13
Applicant: Daisuke Mizutani
Inventor： Daisuke Mizutani
CPC classification number: H05K1/147 , H01L21/76898 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H05K1/0218 , H05K1/141 , H05K3/222 , H05K3/3436 , H05K3/363 , H05K2201/0379 , H05K2201/0715 , H05K2201/09063 , H05K2201/092 , H05K2201/10666 , H05K2201/10734 , H05K2203/167 , Y02P70/613 , H01L2924/00
Abstract: A semiconductor device includes a first circuit base member including a surface having multiple first electrodes formed thereon, a second circuit base member being provided above the first circuit base member and having first through holes and second through holes formed respectively above the first electrodes, a semiconductor package provided above the second circuit base member, and multiple first bumps provided inside the first through holes and the second through holes to connect the first electrodes to the semiconductor package.
Abstract translation: 半导体器件包括：第一电路基体部件，其包括形成有多个第一电极的表面;第二电路基体部件，设置在第一电路基体的上方，并具有分别形成在第一电极上方的第一通孔和第二通孔; 设置在第二电路基体上方的封装，以及设置在第一通孔内的多个第一凸起和第二通孔，以将第一电极连接到半导体封装。
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48.发明授权Substrate for semiconductor package and semiconductor package having the same 有权用于半导体封装的衬底和具有该衬底的半导体封装公开(公告)号：US08698283B2
公开(公告)日：2014-04-15
申请号：US13626116
申请日：2012-09-25
Applicant: SK Hynix Inc.
Inventor： Min Suk Suh
IPC: H01L23/48
CPC classification number: H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/13 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L2224/0554 , H01L2224/05573 , H01L2224/05647 , H01L2224/13021 , H01L2224/13025 , H01L2225/06541 , H01L2225/06551 , H01L2225/06572 , H01L2924/00014 , H01L2924/01078 , H01L2924/078 , H01L2924/15311 , H01L2924/19042 , H01L2924/19043 , H05K1/183 , H05K1/184 , H05K2201/092 , H05K2201/10674 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit.
Abstract translation: 半导体封装包括：衬底，其包括具有第一面的衬底主体和与第一面相对的第二面。 第一穿透电极在第一面和第二面之间通过衬底本体。 绝缘构件设置在第一面上; 并且具有设置在所述绝缘构件内部的第一导电单元的连接构件与所述第一通孔电连接，并且与所述第一导电单元电连接的第二导电单元在所述绝缘构件的侧面露出。 具有第三和第四面的半导体芯片在垂直方向上设置在基板主体的第一面上。 第二穿透电极在第三和第四面之间通过衬底主体并且电连接到第二导电单元。
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49.发明申请SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME 有权用于半导体封装的基板和具有该半导体封装的半导体封装公开(公告)号：US20130020683A1
公开(公告)日：2013-01-24
申请号：US13626116
申请日：2012-09-25
Applicant: HYNIX SEMICONDUCTOR INC.
Inventor： Min Suk SUH
IPC: H01L23/48
CPC classification number: H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/13 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L2224/0554 , H01L2224/05573 , H01L2224/05647 , H01L2224/13021 , H01L2224/13025 , H01L2225/06541 , H01L2225/06551 , H01L2225/06572 , H01L2924/00014 , H01L2924/01078 , H01L2924/078 , H01L2924/15311 , H01L2924/19042 , H01L2924/19043 , H05K1/183 , H05K1/184 , H05K2201/092 , H05K2201/10674 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit.
Abstract translation: 半导体封装包括：衬底，其包括具有第一面的衬底主体和与第一面相对的第二面。 第一穿透电极在第一面和第二面之间通过衬底本体。 绝缘构件设置在第一面上; 并且具有设置在所述绝缘构件内部的第一导电单元的连接构件与所述第一通孔电连接，并且与所述第一导电单元电连接的第二导电单元在所述绝缘构件的侧面露出。 具有第三和第四面的半导体芯片在垂直方向上设置在基板主体的第一面上。 第二穿透电极在第三和第四面之间通过衬底主体并且电连接到第二导电单元。
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公开(公告)号：US20120052695A1
公开(公告)日：2012-03-01
申请号：US12868370
申请日：2010-08-25
Applicant: MYOUNGSOO JEON , ATTALEE SNARR TAYLOR , JOHN JOSEPH CONSOLI
Inventor： MYOUNGSOO JEON , ATTALEE SNARR TAYLOR , JOHN JOSEPH CONSOLI
CPC classification number: H05K3/308 , H01R12/585 , H05K1/116 , H05K3/366 , H05K2201/044 , H05K2201/092 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: An electrical connector assembly includes a circuit board and an electrical connector mounted on the circuit board. The circuit board has a circuit board body having first and second surfaces and through-holes bored between the first and second surfaces. The circuit board has signal traces on internal layers of the circuit board that are generally parallel to the first and second surfaces. Portions of the circuit board body within the through-holes are etched away to expose portions of the signal traces beyond the circuit board body within the corresponding through-hole. The electrical connector includes a housing and signal terminals held by the housing. The signal terminals are received in respective through-holes of the circuit board and engage the corresponding signal traces.
Abstract translation: 电连接器组件包括电路板和安装在电路板上的电连接器。 电路板具有电路板主体，其具有在第一表面和第二表面之间钻孔的第一表面和第二表面以及通孔。 电路板在电路板的内层上具有通常平行于第一和第二表面的信号迹线。 蚀刻掉通孔内的电路板主体的部分，以将信号迹线的部分暴露在对应的通孔内的电路板主体之外。 电连接器包括壳体和由壳体保持的信号端子。 信号端子被接收在电路板的相应通孔中并与相应的信号迹线接合。
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