公开(公告)号：US20170140857A1

公开(公告)日：2017-05-18

申请号：US14943077

申请日：2015-11-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01F5/00

CPC classification number: H01F5/003 ,  H01F3/00

Abstract: Disclosed is a modified magnetic coil structure. A substrate, at least one circuit pattern layer and a permeability enforced ring are included. The substrate is formed of an electrical insulation material, and has a through hole. The circuit pattern layer is formed of an electrically conductive material and configured in the substrate to surround but not contact the through hole. The permeability enforced ring is formed of a high permeability material and provided in the through hole so as to fully cover a sidewall of the through hole. The permeability enforced ring and the substrate form two co-planes in an upper horizontal plane and a lower horizontal plane of the modified magnetic coil structure, respectively. Therefore, the present invention employs the permeability enforced ring to greatly increase magnetic flux density to form a high permeability device, thereby improving the electromagnetic effect and properties of the magnetic coil.

公开(公告)号：US20170032881A1

公开(公告)日：2017-02-02

申请号：US14809295

申请日：2015-07-27

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01F27/28

CPC classification number: H01F27/2804

Abstract: Disclosed is a magnetic excitation coil structure including a magnetic coil sheet formed of a thin film and rolled as a cylindrical body with a hollow hole, and an insulation layer covering the outer surface of the cylindrical body formed by the magnetic coil sheet for protection. The magnetic coil sheet includes a flexible substrate, a dielectric layer attached to the flexible substrate, and a plurality of patterned circuit layers embedded in the flexible substrate and in contact with the dielectric layer. Each patterned circuit layer is separate, and the upper surfaces of the patterned circuit layers and the upper surface of the flexible substrate form a co-plane. The magnetic coil structure provides an electrical function of coil, which is enhanced by the patterned circuit layer due to its high aspect ratio of the electrical circuit, thereby greatly increasing the whole magnetic flux and electromagnetic effect.

Abstract translation: 公开了一种磁激励线圈结构，其包括由薄膜形成的作为具有中空孔的圆筒体并被卷绕的电磁线圈片，以及覆盖由用于保护的电磁线圈片形成的圆筒体的外表面的绝缘层。 磁性线圈片包括柔性衬底，附着到柔性衬底的电介质层和嵌入在柔性衬底中并与电介质层接触的多个图案化电路层。 每个图案化电路层是分离的，并且图案化电路层的上表面和柔性基板的上表面形成共面。 磁线圈结构提供线圈的电功能，由于其电路的高纵横比而由图案化电路层增强，从而大大增加了整个磁通量和电磁效应。

公开(公告)号：US09439292B1

公开(公告)日：2016-09-06

申请号：US14641016

申请日：2015-03-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Jaen-Don Lan ,  Yung-Lin Chia ,  An-Ping Tseng

IPC: H05K1/18 ,  H05K3/06 ,  H05K3/00

CPC classification number: H05K3/064 ,  H01L23/5389 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0008 ,  H05K3/108 ,  H05K3/305 ,  H05K3/425 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2203/166

Abstract: A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 μm so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 μm so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.

Abstract translation: 一种制造具有高密度引脚数的埋入元件的电路板的方法，其中通过图案化干电镀电镀形成在第一电路中的微铜窗容易控制在小于50μm，从而在激光钻孔之后形成的微导电孔 每个具有大大缩小到小于50μm的直径，从而高度增加微通孔的密度，从而便于以高密度引脚数掩埋埋入元件。 此外，通过将相同高度的微通孔设置在一起，可精确地控制掩埋元件的固定位置的光学对准。

公开(公告)号：US20160181188A1

公开(公告)日：2016-06-23

申请号：US14572904

申请日：2014-12-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： TING-HAO LIN ,  CHIAO-CHENG CHANG ,  YI-NUNG LIN

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An ameliorated compound carrier board structure of Flip-Chip Chip-Scale Package has the insulating layer between the carrier board and the substrate in the prior art replaced by an anisotropic conductive film or materials with similar structure. The anisotropic conductive film has conductive particles therein to replace the conductive openings on the insulating layer in the prior art. When compressing the substrate onto the carrier board, the bottom surface of the second electrode pads are compressing the corresponding conductive particles on the second electrical contact pads, causing which to burst, therefore forming high-density compressed areas that conduct the second electrode pads and the second electrical contact pads; the conductive particles outside the high-density compressed area are not burst, forming an insulating film between the substrate and the carrier board: in other words, the anisotropic conductive film provides conduction in a Z direction. The structure can avoid the inaccuracies of distance and size of the conductive openings and the inaccuracy of the contact between the second electrode pads and the second electrical contact pads.

Abstract translation: 翻转芯片尺寸封装的改进的复合载体板结构在现有技术中在载体板和衬底之间具有由各向异性导电膜或具有相似结构的材料代替的绝缘层。 各向异性导电膜在其中具有导电颗粒以替代现有技术中的绝缘层上的导电开口。 当将衬底压缩到载体板上时，第二电极焊盘的底表面压缩第二电接触焊盘上相应的导电颗粒，从而使其破裂，从而形成传导第二电极焊盘的高密度压缩区域 第二电接触垫; 高密度压缩区域外的导电粒子不会突发，在基板和载板之间形成绝缘膜：换句话说，各向异性导电膜在Z方向上提供导电。 该结构可以避免导电开口的距离和尺寸的不准确以及第二电极焊盘和第二电接触焊盘之间的接触的不准确性。

公开(公告)号：US09301405B1

公开(公告)日：2016-03-29

申请号：US14604956

申请日：2015-01-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Jaen-Don Lan ,  Yu-Te Lu ,  Yung-Lin Chia ,  An-Ping Tseng

IPC: H01L21/4763 ,  H05K3/40 ,  H05K3/06 ,  H05K3/00 ,  H05K3/18 ,  H05K3/02 ,  H05K1/09 ,  H05K1/11 ,  H01L21/48

CPC classification number: H05K3/0035 ,  H01L21/4857 ,  H01L2924/01078 ,  H01L2924/014 ,  H05K1/115 ,  H05K3/007 ,  H05K3/064 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/09536

Abstract: A method for manufacturing microthrough-hole includes electroplating a metal layer on a carrier plate, patterning the metal layer to form a first circuit having copper pads, covering the first circuit with a photoresist layer and not covering the copper window between two of the copper pads, etching the metal layer beneath the copper window and removing the photoresist layer, sequentially forming an insulation layer and a second circuit on the first circuit and the copper window, the second circuit layer having a stop pad corresponding to the copper window, removing the carrier plate, upward drilling through the insulation layer between the stop pad and the copper window to form a microthrough-hole beneath the stop pad, and forming a conductive layer in the microthrough-hole to form the microthrough-hole connecting the first and second circuits. The microthrough-hole and its occupied area is greatly reduced, thereby achieving high circuit density.

Abstract translation: 一种用于制造微通孔的方法包括在载体板上电镀金属层，图案化金属层以形成具有铜焊盘的第一电路，用光致抗蚀剂层覆盖第一电路，并且不覆盖两个铜焊盘之间的铜窗 蚀刻铜窗下方的金属层并除去光致抗蚀剂层，在第一电路和铜窗上依次形成绝缘层和第二电路，第二电路层具有对应于铜窗的停止焊盘，移除载体 通过止动垫和铜窗之间的绝缘层向上钻孔，以在止动垫下方形成微通孔，并在微通孔中形成导电层，形成连接第一和第二电路的微通孔。 微通孔及其占用面积大大降低，从而实现高电路密度。

公开(公告)号：US20150355620A1

公开(公告)日：2015-12-10

申请号：US14296422

申请日：2014-06-04

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Shu-Jen Hsiao

IPC: G05B19/05

CPC classification number: G05B19/41865 ,  G05B2219/32096 ,  Y02P90/20

Abstract: A management system includes a product specification data base for storing a plurality of product numbers and product specifications corresponding to the product numbers respectively; a parameter-setting data base for storing principles of parameter-settings; a device specification data base for storing application rules for a plurality of process devices; an execution processor coupled to the product specification data base, the parameter-setting data base and the device specification data base for processing based on the product specification data base, the parameter-setting data base and the device specification data base to produce process recipes of products corresponding to the specification numbers and converting into a plurality of process files adapted to be applied by corresponding process devices; and a process recipe data base coupled to the execution processor for storing the plurality of process files.

Abstract translation: 管理系统包括分别存储与产品编号对应的多个产品编号和产品规格的产品规格数据库; 用于存储参数设置原理的参数设置数据库; 用于存储多个处理装置的应用规则的装置规格数据库; 执行处理器，其基于产品规格数据库，参数设置数据库和设备规格数据库，耦合到产品规格数据库，参数设置数据库和用于处理的设备规格数据库，以产生处理配方 产品对应于规格编号，并转换成适用于相应处理装置应用的多个处理文件; 以及耦合到执行处理器的处理配方数据库，用于存储多个处理文件。

公开(公告)号：US08887386B2

公开(公告)日：2014-11-18

申请号：US13663333

申请日：2012-10-29

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

IPC: H05K3/02

CPC classification number: H05K1/056 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K2201/029 ,  H05K2201/0323 ,  H05K2201/09054 ,  H05K2203/0323 ,  H05K2203/0384 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.

Abstract translation: 一种制造芯片支撑板结构的方法，其包括以下步骤：形成金属基板结构，形成光致抗蚀剂图案，蚀刻金属基板结构以形成桨，去除光致抗蚀剂图案，将绝缘层压靠在桨上， 公开了抛光绝缘层，形成电路层和形成阻焊剂。 金属基板结构是通过将具有两个金属基底层的多层的阻挡层夹在中间而形成的。 在控制下将金属基底结构蚀刻到有效深度，使得如此形成的每个桨具有相同的形状和深度。 因此，本发明的方法可以广泛地应用于通常的批量生产过程，以有效地解决由于芯片支撑板中的深度差异，偏移，位置失配和剥离等现有技术的问题。

公开(公告)号：US08837808B2

公开(公告)日：2014-09-16

申请号：US13721015

申请日：2012-12-20

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Chia-Chi Lo ,  Cheng-Hsiung Yang ,  Jun-Chung Hsu

IPC: G06K9/00 ,  G06T7/00

CPC classification number: H05K1/0269 ,  H05K3/0008 ,  H05K3/225 ,  H05K2201/09927 ,  H05K2201/09936

Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.

Abstract translation: 公开了一种最终缺陷检查的方法，包括使用主机设备准备包括主机，显微镜，条形码扫描仪，支持工具和信号收发器的最终缺陷检查设备来校准轮廓中的原始点 基于由电磁笔产生的多个原始标记位置的电路​​板，使用电磁笔来标记电路板上通过显微镜发现任何缺陷的检查区域上的每个缺陷位置，使用信号收发器接收 并且将每个缺陷位置发送到主机设备，并且使用主机设备基于原始点和每个缺陷位置之间的相对位置来计算废料区域的坐标，以便生成出货文件。

公开(公告)号：US20140177939A1

公开(公告)日：2014-06-26

申请号：US13721015

申请日：2012-12-20

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Chia-Chi Lo ,  Cheng-Hsiung Yang ,  Jun-Chung Hsu

IPC: G06T7/00

CPC classification number: H05K1/0269 ,  H05K3/0008 ,  H05K3/225 ,  H05K2201/09927 ,  H05K2201/09936

Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.

Abstract translation: 公开了一种最终缺陷检查的方法，包括使用主机设备准备包括主机，显微镜，条形码扫描仪，支持工具和信号收发器的最终缺陷检查设备来校准轮廓中的原始点 基于由电磁笔产生的多个原始标记位置的电路​​板，使用电磁笔来标记电路板上通过显微镜发现任何缺陷的检查区域上的每个缺陷位置，使用信号收发器接收 并且将每个缺陷位置发送到主机设备，并且使用主机设备基于原始点和每个缺陷位置之间的相对位置来计算废料区域的坐标，以便生成出货文件。

公开(公告)号：US20140116755A1

公开(公告)日：2014-05-01

申请号：US13663250

申请日：2012-10-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K3/4682 ,  H05K2201/09136 ,  H05K2201/2018

Abstract: A laminate circuit board structure which includes a first circuit metal layer, a first insulation layer, at least one second circuit metal layer, at least one second insulation layer and a support frame is disclosed. The total thickness of the laminate circuit board structure is less than 150 μm. The support frame provided at the outer edge of the co-plane surface formed by the first circuit metal layer and the first insulation layer does not cover the first circuit metal layer, and is formed of at least one metal material. The support frame provides physical support for the entire board structure without influence on the circuit connection so as to prevent the laminate circuit board structure from warping.

Abstract translation: 公开了一种层叠电路板结构，其包括第一电路金属层，第一绝缘层，至少一个第二电路金属层，至少一个第二绝缘层和支撑框架。 叠层电路板结构的总厚度小于150μm。 设置在由第一电路金属层和第一绝缘层形成的共面的外边缘处的支撑框架不覆盖第一电路金属层，并且由至少一种金属材料形成。 支撑框架为整个板结构提供物理支撑，而不影响电路连接，从而防止层压电路板结构翘曲。