公开(公告)号：KR1020090075101A

公开(公告)日：2009-07-08

申请号：KR1020080000872

申请日：2008-01-03

Applicant: 삼성전자주식회사

Inventor： 송승환 ,  공준진 ,  김재홍 ,  조경래 ,  박성정

IPC: G11C29/42 ,  G11C8/10

CPC classification number: G06F11/141 ,  G06F11/1012 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/10 ,  G11C29/00

Abstract: A memory device and an ECC(Error Control Code) decoding method are provided to improve the decoding performance by selectively applying the hard decision decoding or the soft decision decoding. A memory device(100) comprises a memory cell array(110), a decoder(120) and a controller(130). The decoder performs the hard decision decoding of first data and produces the output data and the error information of output data. The controller determines the bit error rate of output data based on the error information. If the bit error rate is greater than the target bit error rate, the controller transmits the additional read command for the soft decision decoding to the memory cell array. The memory cell array transmits the second data to the decoder when receives the additional read command. The decoder performs the soft decision decoding of second data and updates the output data.

Abstract translation: 提供存储器件和ECC（错误控制代码）解码方法，通过选择性地应用硬判决解码或软判决解码来提高解码性能。 存储器装置（100）包括存储单元阵列（110），解码器（120）和控制器（130）。 解码器执行第一数据的硬判决解码，并产生输出数据和输出数据的错误信息。 控制器根据错误信息确定输出数据的误码率。 如果误码率大于目标误码率，则控制器将用于软判决解码的附加读命令发送到存储单元阵列。 当接收附加读命令时，存储单元阵列将第二数据发送到解码器。 解码器执行第二数据的软判决解码并更新输出数据。

公开(公告)号：KR1020090042108A

公开(公告)日：2009-04-29

申请号：KR1020070108026

申请日：2007-10-25

Applicant: 삼성전자주식회사

Inventor： 조경래 ,  박윤동 ,  공준진 ,  이승훈 ,  성정헌 ,  변성재 ,  송승환 ,  유동헌 ,  박성정 ,  은희석

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C2211/5621

Abstract: An apparatus and method of a multi-bit programming in a multi-level memory device is provided to reduce reading failure by using a multi-level programming. A first controller(110) assigns one of 2^N bit threshold voltage states to N bit data. A first controller assigns one to 2^N threshold voltage to a data to be programmed the multi-bit cells respectively. A controller(120) assigns one to 2^N threshold voltage state by a first interval or a second interval. A second controller sets up interval between the second threshold voltage state and the first threshold voltage state the first. A programming part(130) form distribution corresponding to the allocated threshold voltage state is formed in the multi bit cell.

Abstract translation: 提供了一种在多级存储器件中进行多位编程的装置和方法，以通过使用多级编程来减少读取失败。 第一控制器（110）将2 ^ N位阈值电压状态中的一个分配给N位数据。 第一控制器分别向要编程的多位单元的数据分配1至2 N阈值电压。 控制器（120）以一个第一间隔或第二间隔分配一个至2N个阈值电压状态。 第二控制器设置第一阈值电压状态与第一阈值电压状态之间的间隔。 在多位单元中形成与所分配的阈值电压状态对应的编程部分（130）形式分布。

公开(公告)号：KR1020090011230A

公开(公告)日：2009-02-02

申请号：KR1020070074613

申请日：2007-07-25

Applicant: 삼성전자주식회사

Inventor： 공준진 ,  박성정 ,  송승환 ,  김종한 ,  이영환 ,  조경래 ,  조남필 ,  변성재

IPC: G06F12/16 ,  G06F12/00

CPC classification number: H03M13/235 ,  H03M13/6561

Abstract: A device and a method for encoding/decoding codes in reduced time are provided to stably increase the number of bits stored in one memory cell and shorten the time needed for encoding/decoding an ECC(Error Correction Code) by applying a new error correction method to an MLC(Multi-Level Cell). A parallel BCH(Bose, Ray-Chaudhuri, Hocquenghem) code encoder(510) encodes external input information by using a BCH encoding technique. A parallel convolutional code encoder(520) generates an internal encoded bit stream by encoding an input information bit stream in an interleave convolutional encoding technique. A memory(550) stores the codes. A look-ahead Viterbi decoder(530) restores the input information by decoding the code in a look-ahead Viterbi decoding technique. A parallel BCH code decoder(540) restores the input information bit stream by decoding the internal encoded bit stream in a parallel Viterbi decoding technique.

Abstract translation: 提供一种用于在缩短时间内对代码进行编码/解码的装置和方法，以稳定地增加存储在一个存储单元中的位数，并通过应用新的纠错方法缩短对ECC（纠错码）进行编码/解码所需的时间 到MLC（多级单元）。 并行BCH（Bose，Ray-Chaudhuri，Hocquenghem）编码器（510）通过使用BCH编码技术对外部输入信息进行编码。 并行卷积码编码器（520）通过对交织卷积编码技术中的输入信息比特流进行编码来生成内部编码比特流。 存储器（550）存储代码。 先行维特比解码器（530）通过先行维特比解码技术中的代码解码来恢复输入信息。 并行BCH码解码器（540）通过以并行维特比解码技术解码内部编码比特流来恢复输入信息比特流。

公开(公告)号：KR1020090010422A

公开(公告)日：2009-01-30

申请号：KR1020070073509

申请日：2007-07-23

Applicant: 삼성전자주식회사

Inventor： 송승환 ,  채동혁 ,  공준진 ,  이승훈 ,  강동구

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C2211/5634

Abstract: An apparatus for reading data of memory cell and a method thereof are provided to improve efficiency of resource by minimizing cost in circuit design process. A receiving part(110) of an apparatus(150) for reading data of a memory cell receives a predetermined voltage value from a random memory cell(100). A determining part(120) compares a supplied voltage value with a specific voltage section by using a semiconductor device, and determines the supplied voltage value belonging to the specific voltage section according to a compared result. The semiconductor device senses a current in the specific voltage section. If the supplied voltage value belongs to the specific voltage section, a conclusion part(130) determines a data value of the random memory cell as a specific data value mapped in the specific voltage section.

Abstract translation: 提供一种用于读取存储器单元的数据的装置及其方法，以通过最小化电路设计过程中的成本来提高资源的效率。 用于读取存储单元的数据的装置（150）的接收部分（110）从随机存储单元（100）接收预定电压值。 确定部件（120）通过使用半导体器件将供电电压值与特定电压部分进行比较，并根据比较结果确定属于特定电压部分的供电电压值。 半导体器件感测特定电压部分中的电流。 如果提供的电压值属于特定电压部分，则结论部分（130）将随机存储器单元的数据值确定为映射到特定电压部分中的特定数据值。

公开(公告)号：KR1020080101952A

公开(公告)日：2008-11-24

申请号：KR1020070048130

申请日：2007-05-17

Applicant: 삼성전자주식회사

Inventor： 박성정 ,  공준진 ,  이승재 ,  송승환

IPC: H03M13/45

CPC classification number: H04L25/067 ,  H04L27/06 ,  H04L27/22

Abstract: An apparatus and a method for generating a soft decision value generates the soft decision values corresponding to the level of a receiving signal outputted by a low resolution ADC by using metric values previously stored in a storage unit. Metric values computed based on the levels of the transmission signal and the output levels of ADC are received(S610). The metric values corresponding to the level of the receiving signal among the received metric values are selected(S620). When the transmission bit among the selected metric values is the first level, the maximum metric value is detected. When the transmission bit among the selected metric values is the second level, the maximum metric value is detected(S630). The soft decision value is generated based on the difference between the maximum metric value in case the transmission bit is the first level and the maximum metric value in case the transmission bit is the second level(S640).

Abstract translation: 用于产生软判决值的装置和方法通过使用先前存储在存储单元中的度量值，生成与由低分辨率ADC输出的接收信号的电平相对应的软判决值。 接收基于发送信号的电平和ADC的输出电平计算出的公制值（S610）。 选择与接收的度量值中的接收信号的电平对应的度量值（S620）。 当所选度量值中的传输位是第一级时，检测最大度量值。 当所选度量值中的传输比特为第二级时，检测最大度量值（S630）。 基于在传输比特是第一级的情况下的最大度量值与传输比特是第二级的最大度量值之间的差异来生成软判决值（S640）。

公开(公告)号：KR1020080100750A

公开(公告)日：2008-11-19

申请号：KR1020070075857

申请日：2007-07-27

Applicant: 삼성전자주식회사

Inventor： 송승환 ,  공준진 ,  채동혁 ,  이승재 ,  박성정

IPC: G11C16/34 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483

Abstract: A data read apparatus and the method is provided to read data programmed in a memory cell by using two boundary voltages and decodes the read data, and then determines data in the memory cell. A data read apparatus and the method is comprised of steps: comparing the threshold voltage with the first boundary voltage of the memory cell(S610); comparing second boundary voltage having the voltage level higher than the threshold voltage with the first boundary voltage; determining data of the memory cell based on the comparison result of the threshold voltage and the first boundary voltage and threshold voltage and the second boundary voltage(S620); determining data of the memory cell; determining data of the memory cell as disable value if the threshold voltage is voltage between the second boundary voltage and the first boundary voltage(S630).

Abstract translation: 提供数据读取装置和方法，通过使用两个边界电压来读取在存储器单元中编程的数据并解码读取的数据，然后确定存储单元中的数据。 数据读取装置和方法包括步骤：将阈值电压与存储单元的第一边界电压进行比较（S610）; 将具有高于阈值电压的电压电平的第二边界电压与第一边界电压进行比较; 基于阈值电压和第一边界电压与阈值电压和第二边界电压的比较结果，确定存储单元的数据（S620）; 确定存储器单元的数据; 如果阈值电压是第二边界电压和第一边界电压之间的电压，则将存储单元的数据确定为禁用值（S630）。

公开(公告)号：KR1020080098241A

公开(公告)日：2008-11-07

申请号：KR1020070043669

申请日：2007-05-04

Applicant: 삼성전자주식회사

Inventor： 공준진 ,  송승환 ,  이영환 ,  채동혁 ,  조경래 ,  조남필 ,  박성정 ,  강동구

IPC: H03M13/03 ,  H03M13/00

CPC classification number: G06F11/1008

Abstract: An error control code apparatus and a controlling method thereof reduce the latency of decoding and encoding by controlling the number of storage elements according to the error level generated in a generator polynomial channel using an I- interleaved coding scheme. An adjustment control signal generating part(140) generates an ECC(Error Control Code) adjustment control signal based on the channel information. A plurality of ECC encoding control units(110,120) outputs respectively inputted data through the number of storage elements corresponding to the ECC adjustment control signal. An encoding performing unit encodes encoding input data to the number of sub data corresponding to the ECC adjustment control signal by using data outputted from the ECC encoding control units.

Abstract translation: 错误控制代码装置及其控制方法通过使用I-交错编码方案根据在生成多项式信道中生成的错误级别来控制存储元件的数量来减少解码和编码的等待时间。 调整控制信号生成部（140）基于频道信息生成ECC（错误控制代码）调整控制信号。 多个ECC编码控制单元（110,120）通过与ECC调整控制信号相对应的存储元件的数量分别输出输入的数据。 编码执行单元通过使用从ECC编码控制单元输出的数据将编码输入数据编码到与ECC调整控制信号相对应的子数据的数量。

公开(公告)号：KR1020080088050A

公开(公告)日：2008-10-02

申请号：KR1020070030396

申请日：2007-03-28

Applicant: 삼성전자주식회사

Inventor： 공준진 ,  박성정 ,  강동구 ,  채동혁 ,  이승재 ,  조남필 ,  송승환

IPC: G11C29/42 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C29/42 ,  G06F11/1068 ,  G11C11/5628 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: An apparatus and a method for controlling read level are provided to read optimum data from a memory by checking an error rate of decoded data using an ECC decoder. An apparatus for controlling read level includes an ECC(Error Control Code) decoding unit(120), a monitoring unit(130), an error detection unit(140), and a level controller(150). The ECC decoding unit performs ECC decoding on data read from a memory. The monitoring unit monitors a bit error rate based on the ECC decoded data and the read data. The error detection unit determines an error rate of the read data based on the monitored bit error rate. The level controller controls a read level of the memory based on the error rate.

Abstract translation: 提供一种用于控制读取电平的装置和方法，以通过使用ECC解码器检查解码数据的错误率来从存储器读取最佳数据。 用于控制读取电平的装置包括ECC（错误控制代码）解码单元（120），监视单元（130），错误检测单元（140）和电平控制器（150）。 ECC解码单元对从存储器读取的数据执行ECC解码。 监视单元基于ECC解码数据和读取的数据监视比特错误率。 错误检测单元基于所监视的比特错误率来确定读取数据的错误率。 电平控制器基于错误率控制存储器的读取电平。

公开(公告)号：KR100852193B1

公开(公告)日：2008-08-13

申请号：KR1020070042745

申请日：2007-05-02

Applicant: 삼성전자주식회사

Inventor： 공준진 ,  송승환 ,  채동혁 ,  조경래 ,  이승재 ,  조남필 ,  박성정 ,  강동구

IPC: H03M13/29 ,  G11C29/00

CPC classification number: G06F11/1072

Abstract: An error control code apparatus and a method using the same are provided to reduce latency by bypassing a part of ECC(Error Control Code) blocks. An error control code apparatus includes a bypass control signal generation unit(110) and an ECC execution unit(120). The bypass control signal generation unit generates a bypass control signal. The ECC execution unit includes two or more ECC(Error Control Code) decoding blocks and performs an ECC decoding operation by determining a bypassing state of a part of two or more ECC decoding blocks on the basis of the bypass control signal. The bypass signal control generation unit generates the bypass control signal on channel information.

Abstract translation: 提供了一种错误控制代码装置及其使用方法，以通过绕过ECC（错误控制代码）块的一部分来减少等待时间。 错误控制代码装置包括旁路控制信号生成单元（110）和ECC执行单元（120）。 旁路控制信号生成部生成旁路控制信号。 ECC执行单元包括两个或多个ECC（错误控制码）解码块，并且基于旁路控制信号确定两个或更多个ECC解码块的一部分的旁路状态来执行ECC解码操作。 旁路信号控制生成单元生成通道信息的旁路控制信号。

公开(公告)号：KR1020080060657A

公开(公告)日：2008-07-02

申请号：KR1020060135005

申请日：2006-12-27

Applicant: 삼성전자주식회사

Inventor： 송승환 ,  김석필 ,  박윤동 ,  김원주 ,  구준모 ,  조경래 ,  현재웅 ,  변성재

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H01L2029/7858

Abstract: A semiconductor device and a manufacturing method thereof are provided to prevent penetration of conductive materials into a void by blocking the expansion of a void between fins using a semiconductor pillar. A semiconductor substrate comprises a pair of fins(105a,105b) which are used as an active region. A semiconductor pillar(105d) is inserted between the pins in order to connect the pair of pins. A contact plug is formed on the semiconductor pillar so as to be connected to the upper plane of the pair of fins. Wherein, the fin and the semiconductor pillar are formed of the same semiconductor material.

Abstract translation: 提供半导体器件及其制造方法，以防止导电材料通过使用半导体柱阻挡在翅片之间的空隙的膨胀而渗透到空隙中。 半导体衬底包括用作有源区的一对散热片（105a，105b）。 半导体柱（105d）插入在引脚之间以便连接该对引脚。 接触插塞形成在半导体柱上，以便与一对鳍片的上平面连接。 其中，鳍和半导体柱由相同的半导体材料形成。