튜너블 배리어를 구비한 그래핀 트랜지스터
    53.
    发明公开
    튜너블 배리어를 구비한 그래핀 트랜지스터 审中-实审
    石墨晶体管,包括可调壁垒

    公开(公告)号:KR1020150089742A

    公开(公告)日:2015-08-05

    申请号:KR1020140010721

    申请日:2014-01-28

    CPC classification number: H01L29/1606 H01L29/78

    Abstract: 튜너블배리어를구비한그래핀트랜지스터가개시된다. 개시된그래핀트랜지스터는반도체기판상에배치된절연박막과, 상기절연박막상의그래핀층과, 상기그래핀층의일단부와연결된제1전극과, 상기그래핀층의타단부로부터이격되며상기반도체기판과접촉하는제2전극과, 상기그래핀층상의게이트전극을포함한다. 상기반도체기판및 상기그래핀층사이에튜너블에너지배리어가형성된다.

    Abstract translation: 公开了一种包括可调屏障的石墨烯晶体管。 所公开的石墨烯晶体管包括布置在半导体衬底上的绝缘薄膜; 绝缘薄膜上的石墨烯层; 连接到所述石墨烯层的一端的第一电极; 与石墨烯层的另一端分离并与半导体基板接触的第二电极; 和石墨烯层上的栅电极。 在半导体衬底和石墨烯层之间形成能量势垒。

    저마늄을 이용한 반도체 소자의 접합 영역에서의 결함 치유 방법
    57.
    发明公开
    저마늄을 이용한 반도체 소자의 접합 영역에서의 결함 치유 방법 有权
    与GE的半导体器件连接的缺陷治疗方法

    公开(公告)号:KR1020140087549A

    公开(公告)日:2014-07-09

    申请号:KR1020120157977

    申请日:2012-12-31

    Abstract: The present invention relates to a method of repairing a defect in a junction region of a semiconductor device. A p-Ge layer grows on a substrate, and an n+ Ge region is formed on the p-Ge layer through ion implantation or in-situ doping is performed on the upper portion of the p-Ge layer to form the n+ Ge region or an oxide layer is deposited on the p-Ge layer, pattered, etched, and in-situ doped to form the n+ Ge region. After an oxide layer for capping is formed, heat treatment is performed thereon at a temperature of 600-700°C for 1 to 3 hours to deposit an electrode. A leakage current is minimized to improve characteristics of a semiconductor device by relatively reducing deep junction through the heat treatment. The method has advantages in that high integration and refinement of the semiconductor device are realized.

    Abstract translation: 本发明涉及修复半导体器件的接合区域中的缺陷的方法。 p-Ge层在衬底上生长,并且通过离子注入在p-Ge层上形成n + Ge区,或者在p-Ge层的上部进行原位掺杂以形成n + Ge区或 氧化物层沉积在p-Ge层上,图案化,蚀刻和原位掺杂以形成n + Ge区域。 在形成用于封盖的氧化物层之后,在600-700℃的温度下对其进行1至3小时的热处理以沉积电极。 通过相对减少通过热处理的深度接合,使漏电流最小化以改善半导体器件的特性。 该方法具有实现半导体器件的高集成度和精细化的优点。

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