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公开(公告)号：KR1020050067893A
公开(公告)日：2005-07-05
申请号：KR1020030098926
申请日：2003-12-29
Applicant: 전자부품연구원
IPC: H03F1/00
Abstract: 본 발명은 듀얼밴드 파워증폭기 모듈에 관한 것으로서, 칩인덕터와 칩 커패시터들 그리고 RFC를 세라믹 기판을 사용해 3차원적으로 적층 및 형성함으로써 모듈전체의 크기를 줄이도록 하는데, 이를 위해 상호간에 일정거리만큼 이격되도록 제1주파수대역의 파워증폭용MMIC와 제2주파수대역의 파워증폭용MMIC가 실장되는 각각의 위치에 소정의 전극패턴이 형성되며, 해당 주파수대역의 파워증폭용MMIC 각각의 양측에 입력매칭부와 출력매칭부의 소자기준전극패턴이 형성된 최상부레이어부;상기 최상부레이어부의 하부에, 상기 입력매칭부와 출력매칭부의 소자기준전극패턴과 대응되는 소정의 전극패턴이, 형성된 레이어를 원하는 값에 따라 다수개 적층 및 연결하여 형성한, 입/출력매칭레이어부;상기 입/출력매칭레이어부의 하부에 DC바이어스 인가용 RFC( Radio Frequency Choke)스트립 패턴이 형성된 레이어를 다수개 적층 및 연결하여 형성한, RFC 레이어부;상기 RFC레이어부의 하부에 상기 스트립 패턴과 연동하여 DC 바이어스 회로를 구성하는 소정의 바이패스 커패시터 패턴이 형성된 레이어를 다수개 적층 및 연결하여 형성한, 바이패스 레이어부;상기 바이패스 레이어부의 하부에 외부의 입/출력포트와 인터페이스하도록 소정의 전극패턴이 형성된 인터페이스 레이어부를 포함하여 이루어지도록 한다.
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公开(公告)号：KR1020050021620A
公开(公告)日：2005-03-07
申请号：KR1020030057422
申请日：2003-08-20
Applicant: 전자부품연구원
IPC: H04B1/40
Abstract: PURPOSE: A VCO(Voltage Controlled Oscillator) of a dual band mobile terminal is provided to minimize a module so as to have a smaller size than an existing switching device by fabricating the module three-dimensionally. CONSTITUTION: A stack board(200) is formed as a plurality of dielectric boards each with a certain electrode pattern printed thereon are disposed and stacked in a vertical direction according to each stacking type unit element and the circuit disposition pattern of two individual VCOs. Surface-mounted unit elements(301-307) are surface-mounted on the electric pattern of the uppermost dielectric board of the stack board(200). Conductor pads(401-411) are formed from a portion of the side of the uppermost dielectric board to the lowermost dielectric board of the stack board(200) in a vertical direction and electrically connect the stack board(200) and the surface-mounted unit elements(301-307) mutually or connect them with outside.
Abstract translation: 目的：提供双频带移动终端的VCO（压控振荡器），以通过三维地制造模块来最小化模块以使其具有比现有开关器件更小的尺寸。 构成：根据每个堆叠型单元和两个单独的VCO的电路布置图案，堆叠板（200）形成为具有印刷在其上的特定电极图案的多个电介质板沿垂直方向布置和堆叠。 表面安装单元元件（301-307）表面安装在堆叠板（200）的最上层电介质板的电图案上。 导体焊盘（401-411）从最上面的电介质板的一侧到堆叠板（200）的最下面的电介质板的垂直方向形成，并且电连接堆叠板（200）和表面安装 单元元件（301-307）相互连接或将其与外部连接。
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公开(公告)号：KR1020050013730A
公开(公告)日：2005-02-05
申请号：KR1020030052276
申请日：2003-07-29
Applicant: 전자부품연구원
IPC: H04M1/23
CPC classification number: H04B1/50 , H03H7/01 , H04B2001/0491
Abstract: PURPOSE: A stacking switch module used for a dual-band mobile communication terminal is provided to form switching-related unit elements in 3-dimensional structure by stacking and integrating ceramic sheets, thereby reducing a chip part cost and a mounting cost. CONSTITUTION: A switching stack substrate(200) is formed with switching unit elements for switching the first and second communication frequencies having different dual bands and patterns of the switching unit elements, by ceramic sheets which are disposed and stacked in vertical direction while being electrically united together. Surface mounting unit elements(301-308) are mounted on an upper side of the switching stack substrate(200). Conductor walls(401-412) are formed in vertical direction at certain spots on 4 sides of the switching stack substrate(200), and electrically connect the switching unit elements with the surface mounting unit elements(301-308) or with the exterior.
Abstract translation: 目的：提供一种用于双频移动通信终端的堆叠开关模块，通过堆叠和集成陶瓷板形成3维结构的开关相关单元，从而降低芯片部件成本和安装成本。 构成：开关堆叠衬底（200）形成有开关单元元件，用于通过在电连接的情况下沿垂直方向布置和堆叠的陶瓷片来切换具有不同双频带和开关单元元件的图案的第一和第二通信频率 一起。 表面安装单元元件（301-308）安装在开关堆叠基板（200）的上侧。 导体壁（401-412）在开关堆叠基板（200）的4侧的某些点处沿垂直方向形成，并且将开关单元元件与表面安装单元元件（301-308）或外部电连接。
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公开(公告)号：KR200371092Y1
公开(公告)日：2005-01-05
申请号：KR2020040027331
申请日：2004-09-23
Applicant: 전자부품연구원
IPC: H03H7/01
CPC classification number: H03H7/01 , H01P7/065 , H03H9/02574 , H03H9/0561
Abstract: 본 고안은, 듀얼밴드 이동통신단말기용 고주파 스위치 모듈에 관한 것으로서, 인덕터나, 커패시터 등의 스위칭 관련 단위 소자들이 PCB기판에 칩 부품 형태로 실장되는 종래의 2차원적인 구조와는 달리, 인덕터, 커패시터 등의 스위칭 관련 단위 소자들을 세라믹 시트(sheet)를 적층하고 일체화시켜 3차원적인 구조로 형성함으로써, 종래와 같이 칩부품을 사용하지 않아도 되어 칩부품 비용과 그 실장 비용을 절감할 수 있고, 3차원적으로 모듈을 제조할 수 있어 그 크기를 종래의 스위칭 소자보다 최소화할 수 있게 된다.
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公开(公告)号：KR100388279B1
公开(公告)日：2003-06-19
申请号：KR1020010004048
申请日：2001-01-29
Applicant: 전자부품연구원
IPC: H05K1/18
Abstract: PURPOSE: An RF(Radio Frequency) element built-in substrate of MCM(Multi-Chip Module)-C is provided to reduce the number of fabrication processes of the MCM-C by fabricating the MCM-C with active elements and manual elements such as an FET, a transistor, and a diode. CONSTITUTION: A resistance(11) and a capacitor(15) are formed on a ceramic substrate including manual elements. A conductive line(30) is arranged in an inside of the ceramic substrate. Active elements such as a transistor(21) are formed on an upper portion of the ceramic substrate including manual elements. A capacitor and pad pattern(15a) is used as a pad of the active elements and a capacitor(15) mounted in the ceramic substrate. The capacitor and pad pattern(15a) is exposed on an upper surface of the capacitor(15). The transistor(21) is located on the capacitor and pad pattern(15a).
Abstract translation: 目的：提供MCM（多芯片模块）-C的RF（射频）元件内置基板以通过制造具有有源元件和手动元件的MCM-C来减少MCM-C的制造工艺的数量 作为FET，晶体管和二极管。 构成：电阻（11）和电容器（15）形成在包括手动元件的陶瓷基板上。 导线（30）布置在陶瓷基板的内部。 诸如晶体管（21）的有源元件形成在包括手动元件的陶瓷基板的上部上。 电容器和焊盘图案（15a）用作有源元件的焊盘和安装在陶瓷基板中的电容器（15）。 电容器和焊盘图案（15a）暴露在电容器（15）的上表面上。 晶体管（21）位于电容器和焊盘图案（15a）上。
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Patent Agency Ranking
公开(公告)号：KR1020030004474A
公开(公告)日：2003-01-15
申请号：KR1020010039967
申请日：2001-07-05
Applicant: 전자부품연구원
IPC: G01R27/28
Abstract: PURPOSE: A device for calibrating stack elements, a method for manufacturing the same and a method for measuring a high frequency characteristics by using the same are provided to eliminate the effect of a via hole and accurately measure a high frequency characteristic by making the structure which is similar to an object to be measured. CONSTITUTION: A device(300) for calibrating stack elements includes an impedance pattern layer located at the same height of an incorporated device to be measured and printed thereon an impedance pattern(310) to performing the calibration of the incorporated device, a via hole layer stacked on the impedance pattern layer and having the same height of a via hole(320) of the incorporated device and a plurality of conductive pads(330) stacked on the via hole layer and connected to the impedance pattern(310) through the via hole(320), wherein the device(300) is calibrated to the impedance pattern(310) corresponding to the position of the incorporated device by contacting a measurement device to perform the calibration at the conductive pads(330).
Abstract translation: 目的：提供一种用于校准堆叠元件的装置，其制造方法以及通过使用它们来测量高频特性的方法，以消除通孔的影响并精确地测量高频特性， 类似于要测量的对象。 构成：用于校准堆叠元件的装置（300）包括阻抗图案层，该阻抗图案层位于被测量的并入装置的相同高度并在其上印刷有阻抗图案（310），以执行所结合的装置的校准，通孔层 堆叠在阻抗图案层上并且具有与所结合的器件的通孔（320）相同的高度和堆叠在通孔层上并通过通孔连接到阻抗图案（310）的多个导电焊盘（330） （320），其中通过接触测量装置在所述导电焊盘（330）处执行所述校准，所述装置（300）被校准为对应于所结合的装置的位置的所述阻抗图案（310）。
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公开(公告)号：KR1020020063404A
公开(公告)日：2002-08-03
申请号：KR1020010004048
申请日：2001-01-29
Applicant: 전자부품연구원
IPC: H05K1/18
CPC classification number: H05K1/185 , H05K1/0237
Abstract: PURPOSE: An RF(Radio Frequency) element built-in substrate of MCM(Multi-Chip Module)-C is provided to reduce the number of fabrication processes of the MCM-C by fabricating the MCM-C with active elements and manual elements such as an FET, a transistor, and a diode. CONSTITUTION: A resistance(11) and a capacitor(15) are formed on a ceramic substrate including manual elements. A conductive line(30) is arranged in an inside of the ceramic substrate. Active elements such as a transistor(21) are formed on an upper portion of the ceramic substrate including manual elements. A capacitor and pad pattern(15a) is used as a pad of the active elements and a capacitor(15) mounted in the ceramic substrate. The capacitor and pad pattern(15a) is exposed on an upper surface of the capacitor(15). The transistor(21) is located on the capacitor and pad pattern(15a).
Abstract translation: 目的：提供MCM（多芯片模块）-C的内置RF（射频）元件，以通过用有源元件和手动元件制造MCM-C来减少MCM-C的制造工艺数量 作为FET，晶体管和二极管。 构成：在包括手动元件的陶瓷基板上形成电阻（11）和电容器（15）。 导电线（30）布置在陶瓷衬底的内部。 诸如晶体管（21）的有源元件形成在包括手动元件的陶瓷基板的上部。 电容器和焊盘图案（15a）用作有源元件的焊盘和安装在陶瓷衬底中的电容器（15）。 电容器和焊盘图案（15a）暴露在电容器（15）的上表面上。 晶体管（21）位于电容器和焊盘图案（15a）上。
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公开(公告)号：KR100293307B1
公开(公告)日：2001-10-25
申请号：KR1019980016883
申请日：1998-05-12
Applicant: 전자부품연구원
IPC: H01F27/00
Abstract: PURPOSE: A stacked ferrite inductor and method for manufacturing the same is provided to easily estimate an inductance value by changing turns of coil, while maintaining cross section occupied by the coil constant. CONSTITUTION: A stacked ferrite inductor comprises a first ferrite sheet unit having a plurality of first ferrite sheets(51,53,56,58) having via holes(512,532,562) connected to electrode patterns(511,531,561,581); a second ferrite sheet unit having a plurality of second ferrite sheets(52,54,55,57) having via holes(522,542,552,572), wherein the second ferrite sheets having no electrode patterns are inserted between first ferrite sheets; a conductive paste filling the via holes of first and second ferrite sheets so as to interconnect the electrode patterns; and a third ferrite sheet unit having a plurality of third ferrite sheets(1,2) disposed onto and beneath the first ferrite sheet unit, wherein third ferrite sheets have no electrode patterns.
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公开(公告)号：KR100294979B1
公开(公告)日：2001-07-12
申请号：KR1019980021898
申请日：1998-06-12
Applicant: 전자부품연구원
Abstract: 다중 대역 세라믹 칩 안테나를 개시한다. 이 다중 대역 세라믹 칩 안테나는 세라믹 유전체를 재료로 하여 직육면체로 형성되는 본체와, 본체 내부에 독립적으로 형성되는 다수의 헬리컬 도체를 포함한다. 다수의 헬리컬 도체는 나선 형상으로 형성된 하나 이상의 메인 헬리컬 도체와, 각 메인 헬리컬 도체 내부에 나선형으로 형성되는 다수의 서브 헬리컬 도체를 포함한다. 각 헬리컬 도체의 나선 회전축은 본체의 밑면과 옆면에 각각 평행하다. 각 헬리컬 도체의 길이 등을 다르게 형성함으로서 각 헬리컬 도체의 사용 주파수 대역이 달라지게 된다. 따라서 다수의 주파수 대역을 사용할 수 있으며, 크기가 작아서 휴대 단말기에 내장이 가능하고, 또한 비교적 넓은 밴드 폭을 갖는다.
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公开(公告)号：KR1020010036982A
公开(公告)日：2001-05-07
申请号：KR1019990044238
申请日：1999-10-13
Applicant: 전자부품연구원
IPC: H01G4/30
Abstract: PURPOSE: A high frequency condenser for ceramic laminated module is provided to improve the capacitance characteristics and the high frequency characteristics by minimizing the condenser area and by reducing the signal transmission distance by the via contact. CONSTITUTION: The high frequency condenser for ceramic laminated module has the via contacts(18) on the center of the electrode patterns(10a,10b,10c,10d) and omits the pad of the electrode patterns. The multiple electrode patterns are connected alternatively. The electrode pattern has the square shaped plane structure where the capacitance is charged on that area and two holes on the center position of each electrode pattern. One hole of each electrode pattern is alternatively connected to the holes of adjacent electrode patterns, and the other hole of each electrode pattern is connected to the insulator pattern. The insulator patterns(14a,14b,14c,14d) are laminated between electrode patterns. The via holes(16a,16b,16c,16d) are formed on each insulator pattern and on each electrode pattern. All via holes are filled by conductive material to form the via contact.
Abstract translation: 目的：提供陶瓷层叠模块的高频电容器，通过最小化电容器面积和通过通孔接点减小信号传输距离，提高电容特性和高频特性。 构成：用于陶瓷层叠模块的高频电容器在电极图案（10a，10b，10c，10d）的中心具有通孔触点（18），并省略电极图案的焊盘。 多个电极图案交替连接。 电极图案具有方形平面结构，其中电容在该区域上充电，并且在每个电极图案的中心位置具有两个孔。 每个电极图案的一个孔替代地连接到相邻电极图案的孔，并且每个电极图案的另一个孔连接到绝缘体图案。 绝缘体图案（14a，14b，14c，14d）层叠在电极图案之间。 通孔（16a，16b，16c，16d）形成在每个绝缘体图案上和每个电极图案上。 所有通孔由导电材料填充以形成通孔接触。
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