公开(公告)号：AU2019376835A1

公开(公告)日：2021-04-22

申请号：AU2019376835

申请日：2019-11-05

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  RECKTENWALD MARTIN ,  SCHMIDT DONALD WILLIAM ,  SLEGEL TIMOTHY ,  PURANIK ADITYA NITIN ,  FARRELL MARK ,  JACOBI CHRISTIAN ,  BRADBURY JONATHAN ,  ZOELLIN CHRISTIAN GERHARD

IPC: G06F9/30 ,  G06F9/38

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：HUE046174T2

公开(公告)日：2020-02-28

申请号：HUE15763327

申请日：2015-09-14

Applicant: IBM

Inventor： HELLER LISA ,  BUSABA FADI ,  BRADBURY JONATHAN ,  FARRELL MARK ,  GREINER DAN ,  KUBALA JEFFREY ,  OSISEK DAMIAN ,  SLEGEL TIMOTHY ,  SCHMIDT DONALD

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/46 ,  G06F9/48

公开(公告)号：CA2800632C

公开(公告)日：2019-03-05

申请号：CA2800632

申请日：2010-11-08

Applicant: IBM

Inventor： GREINER DAN ,  GAINEY CHARLES ,  CRADDOCK DAVID ,  CONESKI ANTHONY ,  GLENDENING BETH ,  FARRELL MARK ,  GREGG THOMAS ,  NJOKU-CHARLES UGOCHUKWU

IPC: G06F13/28 ,  G06F13/38

Abstract: An adapter is enabled for use. The enabling includes assigning one or more address spaces to the adapter, based on a request. For each address space assigned to the adapter, a corresponding device table entry is assigned. When the adapter is no longer needed, it is disabled and the assigned device table entries become available.

公开(公告)号：RU2670909C9

公开(公告)日：2018-12-12

申请号：RU2016127444

申请日：2015-03-16

Applicant: IBM

Inventor： GREJNER DEN ,  FARRELL MARK ,  OSISEK DEJMIAN LEO ,  SHMIDT DONALD UILLYAM ,  BUSABA FADI YUSUF ,  KUBALA DZHEFFRI POL ,  BREDBERI DZHONATAN DEJVID ,  KHELLER LAJZA KRANTON ,  SLEGEL TIMOTI

IPC: G06F9/46

Abstract: Изобретениеотноситсяк компьютернойсистемеи копьютерно-реализуемомуспособувосстановленияконтекстапотокав конфигурации. Техническийрезультатзаключаетсяв обеспеченииподдержкимногопотоковойобработкиданных. Системасодержитконфигурацию, включающуюядро, конфигурируемоемеждурежимомединственногопотока (ST) имногопоточным (МТ) режимом, причемрежим ST адресуетпервичныйпоток, арежимМТадресуетпервичныйпоток, атакжеодинилинескольковторичныхпотоковнасовместноиспользуемыхресурсахядра, исредствомногопоточности, конфигурируемоедляуправленияиспользованиемконфигурациидлявыполненияспособа, содержащегодеактивациюодногоилинесколькихвторичныхпотоковнаоснованиипереключенияотрежимаМТк режиму ST вответнасбросилидеактивациюконфигурации, производствозапроса, привыполнениив режиме ST, назаданныйпоследниммаксимальныйуровеньМТдлявыявлениязаданногопоследнимпрограммно-задаваемогомаксимального ID потокаконфигурации, иполучениеконтекстапотокаодногоилинесколькихвторичныхпотоковпутемвыполнениякомандызаданияМТдлявозобновлениярежимаМТи получениядоступак контекступотокаодногоилинесколькихвторичныхпотоковнаоснованиинахожденияв возобновленномрежимеМТ. 2 н. и 13 з.п. ф-лы, 17 ил., 1 табл.

公开(公告)号：AU2015340844B2

公开(公告)日：2018-10-18

申请号：AU2015340844

申请日：2015-10-21

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  ALEXANDER KHARY JASON ,  BUSABA FADI YUSUF ,  FARRELL MARK ,  RELL JR JOHN GILBERT

IPC: G06F9/30

Abstract: Execution of threads in a processor core is controlled. The processor core supports simultaneous multi-threading (SMT) such that there can be effectively multiple logical central processing units (CPUs) operating simultaneously on the same physical processor hardware. Each of these logical CPUs is considered a thread. In such a multi-threading environment, it may be desirous for one thread to stop other threads on the processor core from executing. This may be in response to running a critical sequence or other sequence that needs the processor core resources or is manipulating processor core resources in a way that other threads would interfere with its execution.

公开(公告)号：AU2015238665B2

公开(公告)日：2018-01-18

申请号：AU2015238665

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES

IPC: G06F9/50 ,  G06F9/38

Abstract: A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

公开(公告)号：ZA201606254B

公开(公告)日：2017-08-30

申请号：ZA201606254

申请日：2016-09-09

Applicant: IBM

Inventor： FARRELL MARK ,  BUSABA FADI YUSUF ,  HELLER LISA CRANTON

Abstract: According to one aspect, a computer system includes a configuration with a machine enabled to operate in a single thread (ST) mode and a multithreading (MT) mode. In addition, the machine includes physical threads. The machine is configured to perform a method that includes issuing a start-virtual-execution (start-VE) instruction to dispatch a guest entity having multiple logical threads on the core. The guest entity includes all or a part of a guest virtual machine (VM), and issuing is performed by a host running on one of the physical threads on the core in the ST mode. The executing of the start-VE instruction by the machine includes mapping each of the logical threads to a corresponding one of the physical threads, initializing each of the mapped physical threads with a state of the corresponding logical thread, and starting execution of the guest entity on the core in MT mode.

公开(公告)号：BR112014017826A2

公开(公告)日：2017-06-20

申请号：BR112014017826

申请日：2012-11-13

Applicant: IBM

Inventor： GAINEY CHARLES JR ,  KUBALA JEFFREY PAUL ,  FARRELL MARK ,  SCHMIDT DONALD WILLIAM ,  ROGERS ROBERT ,  PIERCE BERNARD ,  MULDER JAMES

公开(公告)号：AU2015330266A1

公开(公告)日：2017-03-09

申请号：AU2015330266

申请日：2015-09-14

Applicant: IBM

Inventor： FARRELL MARK ,  HELLER LISA ,  KUBALA JEFFREY PAUL ,  SCHMIDT DONALD WILLIAM ,  GREINER DAN ,  SLEGEL TIMOTHY ,  BUSABA FADI YUSUF ,  OSISEK DAMIAN ,  BRADBURY JONATHAN DAVID ,  LEHNERT FRANK ,  NERZ BERND ,  JACOBI CHRISTIAN

IPC: G06F9/455 ,  G06F9/48

Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.

公开(公告)号：ES2598816T3

公开(公告)日：2017-01-30

申请号：ES12866318

申请日：2012-11-13

Applicant: IBM

Inventor： GAINEY CHARLES ,  KUBALA JEFFREY ,  FARRELL MARK ,  SCHMIDT DONALD ,  MULDER JAMES ,  PIERCE BERNARD ,  ROGERS ROBERT

IPC: G06F9/46 ,  G06F9/54 ,  G06F11/14

Abstract: Un sistema informático (200) para facilitar el procesamiento en un entorno informático, comprendiendo dicho sistema informático: una memoria; y un procesador en comunicación con la memoria, en donde el sistema informático está configurado para realizar un método, comprendiendo dicho método: que un programa obtenga una indicación de una funcionalidad de margen de advertencia instalada (700) dentro del entorno informático, donde la funcionalidad de margen de advertencia proporciona al programa un período de gracia de margen de advertencia para realizar una función; que el programa inicie, basándose en la obtención de la indicación de que la funcionalidad de margen de advertencia está instalada, la inscripción del programa en el registro de la funcionalidad de margen de advertencia (702), comprendiendo la inscripción en el registro una petición no solicitada de inscripción en el registro que indica que el programa entiende un protocolo de la funcionalidad de margen de advertencia y pretende participar en la funcionalidad de margen de advertencia; que el programa reciba una notificación de margen de advertencia que indica que ha comenzado el período de gracia de margen de advertencia, siendo la inscripción del programa en el registro de la funcionalidad de margen de advertencia un requisito previo para recibir la notificación de margen de advertencia, en donde si el programa no está registrado, entonces no se ofrece período de gracia; y que el programa, basándose en la notificación de margen de advertencia, al menos inicie la función dentro del período de gracia de margen de advertencia.