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公开(公告)号：LT3123326T
公开(公告)日：2018-07-10
申请号：LT15711701
申请日：2015-03-16
Applicant: IBM
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公开(公告)号：AU2015238662B8
公开(公告)日：2018-04-19
申请号：AU2015238662
申请日：2015-03-16
Applicant: IBM
Inventor： HELLER LISA CRANTON , BRADBURY JONATHAN DAVID , KUBALA JEFFREY PAUL , FARRELL MARK , OSISEK DAMIAN LEO , GREINER DAN , SLEGEL TIMOTHY , BUSABA FADI YUSUF , SCHMIDT DONALD WILLIAM , GAINEY JR CHARLES
Abstract: A computer system includes a virtual machine (VM) configuration with one or more cores. Each core is enabled to operate in a single thread (ST) mode or a multithreading (MT) mode. The ST mode consists of a single thread and the MT mode consists of a plurality of threads on shared resources of a respective core. The computer system includes a core-oriented system control area (COSCA) having a common area representing all of the cores of the VM configuration and separate core description areas for each of the cores in the VM configuration. Each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread.
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公开(公告)号：CA3036108A1
公开(公告)日：2018-04-05
申请号：CA3036108
申请日：2017-09-26
Applicant: IBM
Inventor： GREINER DAN , SLEGEL TIMOTHY , ZOELLIN CHRISTIAN , NERZ BERND , VISEGRADY TAMAS
IPC: G06F7/58
Abstract: An instruction configured to perform a plurality of functions is executed. Based on a function code associated with the instruction having a selected value, one or more inputs of the instruction are checked to determine which one or more functions of the plurality of functions are to be performed. Based on a first input of the one or more inputs having a first value, a function of providing raw entropy is performed, in which the providing of raw entropy includes storing a number of raw random numbers. Further, based on a second input of the one or more inputs having a second value, a function of providing conditioned entropy is provided, in which the providing of conditioned entropy includes storing a number of conditioned random numbers.
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公开(公告)号：BR112012032854A2
公开(公告)日：2018-02-27
申请号：BR112012032854
申请日：2010-11-08
Applicant: IBM
Inventor： BETH GLENDENING , CRADDOCK DAVID , GREINER DAN , MARK FARRELL , THOMAS GREGG
IPC: G06F9/46
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公开(公告)号：ZA201605466B
公开(公告)日：2017-08-30
申请号：ZA201605466
申请日：2016-08-05
Applicant: IBM
Inventor： GAINEY JR CHARLES (DECEASED) , SLEGEL TIMOTHY , HELLER LISA CRANTON , BRADBURY JONATHAN DAVID , KUBALA JEFFREY PAUL , BUSABA FADI YUSUF , SCHMIDT DONALD WILLIAM , OSISEK DAMIAN LEO , FARRELL MARK , GREINER DAN
Abstract: Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.
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Patent Agency Ranking
公开(公告)号：SI2834736T1
公开(公告)日：2017-04-26
申请号：SI201230900
申请日：2012-11-22
Applicant: IBM
Inventor： GREINER DAN , JACOBI CHRISTIAN , SLEGEL TIMOTHY
IPC: G06F9/00
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公开(公告)号：SG11201701614WA
公开(公告)日：2017-03-30
申请号：SG11201701614W
申请日：2015-09-14
Applicant: IBM
Inventor： FARRELL MARK , HELLER LISA , KUBALA JEFFREY PAUL , SCHMIDT DONALD WILLIAM , GREINER DAN , SLEGEL TIMOTHY , BUSABA FADI YUSUF , OSISEK DAMIAN , BRADBURY JONATHAN DAVID , LEHNERT FRANK , NERZ BERND , JACOBI CHRISTIAN
Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.
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58.发明专利
公开(公告)号：MX2016012529A
公开(公告)日：2016-12-20
申请号：MX2016012529
申请日：2015-03-16
Applicant: IBM
Inventor： FARRELL MARK , GREINER DAN , SCHMIDT DONALD WILLIAM , OSISEK DAMIAN LEO , GAINEY JR CHARLES , FADI YUSUF BUSABA , JEFFREY PAUL KUBALA , JONATHAN DAVID BRADBURY , LISA CRANTON HELLER , TIMOTHY SLEGEL
Abstract: Un sistema de computadora incluye una configuración con un núcleo configurable entre un modo de subprocesamiento individual (ST) y un modo de subprocesamiento múltiple (MT). El modo ST dirige un subproceso primario y el modo MT dirige el subproceso primario y uno o más subprocesos secundarios en recursos compartidos del núcleo. Se configura un servicio de subprocesamiento múltiple para controlar la utilización de la configuración para llevar a cabo un método que incluye acceder al subproceso primario en el modo ST utilizando un valor de dirección de núcleo y conmutar del modo ST al modo MT. Se accede al subproceso primario o uno del uno o más subprocesos secundarios en el modo MT utilizando un valor de dirección expandida, en donde el valor de dirección expandida incluye el valor de dirección de núcleo concatenado con un valor de dirección de subproceso.
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公开(公告)号：CA2701093C
公开(公告)日：2016-10-11
申请号：CA2701093
申请日：2009-01-07
Applicant: IBM
Inventor： GREINER DAN , SLEGEL TIMOTHY
IPC: G06F9/312
Abstract: In a method of operating a computer system there is provided a facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) in saved in a register.
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公开(公告)号：BRPI0906424A2
公开(公告)日：2016-10-11
申请号：BRPI0906424
申请日：2009-01-07
Applicant: IBM
Inventor： GREINER DAN , SLEGEL TIMOTHY
IPC: G06F9/312
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