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公开(公告)号：SE0402045L
公开(公告)日：2004-08-18
申请号：SE0402045
申请日：2004-08-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGEL BERNHARD , GREGORIUS PETER
Abstract: A CDR circuit arrangement, for example for a transceiver module, features a data recovery unit ( 4 ) for the recovery of the data contained in a received signal (DATA) by scanning this received data signal, and a phase evaluation unit for the determination of a suitable phase position for the scanning carried out by the data recovery unit ( 4 ). The phase evaluation unit comprises a scanning device ( 1 ) for the oversampling of a the received data signal (DATA) in accordance with several different scanning phases (P 0 -P 6 ), a phase detector device ( 2 ) for the evaluation of the scanning values (A 0 -A 6 ) accordingly prepared by the scanning device ( 1 ), in order thereby to derive intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ), which classify the phase error during the scanning of the data signal by the scanning device ( 1 ) in respect of its size and direction of deviation, as well as a filter device ( 3 ), in order to subject the intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ) generated by the phase detector device ( 2 ) to a weighted filtering process. In this situation, a setting signal (DeltaP) is generated by the filter device ( 3 ) for the subsequent regulation and control of the scanning phases (P 0 -P 6 ) of the scanning device ( 1 ).
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公开(公告)号：DE10258406A1
公开(公告)日：2004-07-15
申请号：DE10258406
申请日：2002-12-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LINDT PAUL , GREGORIUS PETER
Abstract: The method involves oversampling the digital signal with a sampling signal derived from the signal to derive two groups of sampling values per data signal data bit, evaluating the first group to determine a phase deviation of the signal relative to the digital signal and generate a first phase correction signal and evaluating the second group to determine a coarse phase deviation and generate a second phase correction signal The method involves oversampling the digital signal (D) with a sampling signal derived from the digital signal to derive first and second groups of sampling values per data bit of the data signal, evaluating the first group to determine a phase deviation of the signal relative to the digital signal and to generate a first phase correction signal (pdo) and evaluating the second group to determine a coarse phase deviation of the signal relative to the digital signal and to generate a second phase correction signal (pherr). Independent claims are also included for the following: (a) a phase detector arrangement (b) a phase control loop for a phase detector arrangement (c) and a circuit for clock and data recovery from a digital signal with a phase control loop.
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公开(公告)号：DE10137150A1
公开(公告)日：2003-02-27
申请号：DE10137150
申请日：2001-07-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER , HANNEBERG ARMIN , LAASER PETER
Abstract: A line driver ( 3 ) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors ( 14, 15 ) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors ( 16, 17 ), each with the differential pair transistors ( 14, 15 ) forming a cascode circuit, onto the data transmission line ( 8, 9 ) connected to the line driver ( 3 ). For reproducing the behaviour of the differential pair a replica differential pair with replica differential pair transistors ( 18, 19 ) is provided, generating replica impulses corresponding to the transmission impulses, which replica impulses can be fed via replica cascode transistors ( 20, 21 ) to a hybrid integrated circuit ( 6 ) for effecting echo compensation in relation to impulses received via the data transmission line ( 8, 9 )
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公开(公告)号：DE10110140C1
公开(公告)日：2003-02-06
申请号：DE10110140
申请日：2001-03-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER
IPC: H03K17/082 , H03K17/687 , H02H7/20 , G05F3/26 , G01R19/165 , H02H9/02 , H04B3/36
Abstract: A detection circuit is described which is configured, in particular, for line drivers for ascertaining the presence of an overshooting of a current flowing through a line above a predetermined value. The detection circuit has two current mirrors, in each case the input of one current mirror being connected to the output of the other current mirror. If the current feeds one current mirror, then an overshooting of the predetermined value can be ascertained on the basis of an output signal of the other current mirror.
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公开(公告)号：DE10124177A1
公开(公告)日：2002-11-28
申请号：DE10124177
申请日：2001-05-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GAZSI LAJOS , GREGORIUS PETER , RENNER MARTIN , DUDA THOMAS , HINZ TORSTEN
Abstract: The signal attenuated by transmission, is amplified. Noise, comprising high frequencies above the symbolic transmission rate, is filtered out. The analog signal is made discrete using a high sampling rate ADC (3). Cable approximation is carried out, using a digitally-implemented cable approximation filter (7), to obtain a reconstituted signal. The original data is recovered from it. An Independent claim is included for the signal restoration equipment
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Patent Agency Ranking
公开(公告)号：DE102005042269B4
公开(公告)日：2008-09-18
申请号：DE102005042269
申请日：2005-09-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER , RUCKERBAUER HERMANN , SAVIGNAC DOMINIQUE , SICHERT CHRISTIAN , WALLNER PAUL
IPC: G11C7/22
Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.
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公开(公告)号：DE10258406B4
公开(公告)日：2007-10-31
申请号：DE10258406
申请日：2002-12-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LINDT PAUL , GREGORIUS PETER
Abstract: The method involves oversampling the digital signal with a sampling signal derived from the signal to derive two groups of sampling values per data signal data bit, evaluating the first group to determine a phase deviation of the signal relative to the digital signal and generate a first phase correction signal and evaluating the second group to determine a coarse phase deviation and generate a second phase correction signal The method involves oversampling the digital signal (D) with a sampling signal derived from the digital signal to derive first and second groups of sampling values per data bit of the data signal, evaluating the first group to determine a phase deviation of the signal relative to the digital signal and to generate a first phase correction signal (pdo) and evaluating the second group to determine a coarse phase deviation of the signal relative to the digital signal and to generate a second phase correction signal (pherr). Independent claims are also included for the following: (a) a phase detector arrangement (b) a phase control loop for a phase detector arrangement (c) and a circuit for clock and data recovery from a digital signal with a phase control loop.
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公开(公告)号：DE102005001894A1
公开(公告)日：2006-08-03
申请号：DE102005001894
申请日：2005-01-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WALLNER PAUL , GREGORIUS PETER , SCHLEDZ RALF
Abstract: The synchronous parallel-series converter has first shift register (SRod) which accepts odd-numbered part (D1od(1/8)) of input signal synchronously to rear and front flank of the clock pulse (clkhri) with a first load signal (odloadi) and lets it serially pass as first one-bit signal sequence (D2od(1/2)). A second shift register (SRev) accepts an even-numbered part (D1ev(1/8)) of input signal synchronously to front or rear flank of the clock pulse with a second load signal (evloadi) and lets it serially pass as a second one-bit signal sequence (D2ev(1/2)). A fusion unit (M) accepts the first one-bit signal sequence from first shift register and second one-bit signal sequence from the second shift register. The clock pulse and the first one-bit signal sequence merges synchronously with the rear or front flank of the clock pulse. The second one-bit signal sequence merges synchronously with the front or rear flank of the clock pulse to output signal (D3(1/1)). An independent claim is also included for the use of the synchronous parallel-series converter.
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公开(公告)号：DE102005055185A1
公开(公告)日：2006-06-08
申请号：DE102005055185
申请日：2005-11-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： RUCKERBAUER HERMANN , BACHA ABDALLAH , SICHERT CHRISTIAN , SAVIGNAC DOMINIQUE , GREGORIUS PETER , WALLNER PAUL
IPC: G11C7/22
Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
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公开(公告)号：DE102004037162A1
公开(公告)日：2006-03-23
申请号：DE102004037162
申请日：2004-07-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER , DA DALT NICOLA
Abstract: A method and a device for generating a clock signal (F out ) are provided, wherein a digital phase difference signal (X) is formed depending on a phase difference between a reference clock signal (F in ) and a feedback signal (F fb ) derived from the clock signal (F out ) and wherein the digital phase difference signal (X) is digitally filtered, in order to form a digital filtered phase difference signal (U). A digitally controlled oscillator ( 5 ) is activated by a digital control signal dependent on the digital filtered phase difference signal (U) to generate the clock signal (F out ). With a device of this kind clock signals with frequencies in the gigahertz range can be generated with a minimum of analog circuit parts.
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