公开(公告)号：FR2838866A1

公开(公告)日：2003-10-24

申请号：FR0205073

申请日：2002-04-23

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  SKOTNICKI THOMAS

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/68 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/40 ,  H01L21/70 ,  H01L27/108

Abstract: Fabrication of an integrated electronic component comprises: producing an initial structure (SI) incorporating volumes of respective materials forming a definite pattern (M) on a first substrate; transferring the pattern to a second substrate (200); and producing, on the second substrate surface, an additional structure by using the volumes of the materials of the pattern as alignment markers. Fabrication of an integrated electronic component comprises: (a) producing, on the surface of a first substrate (100), an initial structure (SI) incorporating volumes of respective materials, at least part of the volumes forming a definite pattern (M); (b) transferring at least a part of the initial structure (SI) comprising the pattern of the first substrate (100) to a second substrate (200); and (c) producing, on the surface of the second substrate (200), an additional structure by using at least some of the volumes of the materials of the pattern (M) as alignment markers. Independent claims are given for: (i) an integrated electronic component obtained by the invented process; and (ii) an electronic device comprising a transistor, or a diode, or a dynamic random access memory (DRAM) element.

公开(公告)号：FR2830984A1

公开(公告)日：2003-04-18

申请号：FR0113375

申请日：2001-10-17

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE ,  TORRES JOAQUIM

IPC: H01L21/762 ,  H01L21/764

公开(公告)号：FR2821208B1

公开(公告)日：2003-04-11

申请号：FR0102347

申请日：2001-02-21

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  FERREIRA PAUL

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/52 ,  H01L21/8239

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

公开(公告)号：FR2830124A1

公开(公告)日：2003-03-28

申请号：FR0112377

申请日：2001-09-26

Applicant: ST MICROELECTRONICS SA

Inventor： PIAZZA MARC ,  CORONEL PHILIPPE

IPC: H01L21/8242 ,  H01L27/108

Abstract: Two trenches are dug into an upper insulating layer in such a way that one trench has a width twice that of another trench having a minimum width. The neighboring trenches are separated by a minimum interval and each of the trenches are surrounded with two of the other trenches, respectively. An Independent claim is also included for a dynamic random access memory.

公开(公告)号：FR2819633A1

公开(公告)日：2002-07-19

申请号：FR0100691

申请日：2001-01-18

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  PIAZZA MARC ,  LEVERD FRANCOIS

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method for the integration of a Dynamic Random Access Memory (DRAM), allowing a freedom from the alignment margins inherent in the photoengraving of the upper electrode for the contact passage of the bit line, the retreat of the upper electrode being auto-aligned on the lower electrode, consists of: (a) forming a topographical difference at the spot (A) where the opening for the upper electrode is to be realised; (b) depositing a layer of non-doped polysilicon on the upper electrode; (c) producing an implantation of strongly inclined doping in this layer; (d) selectively engraving the non-doped part of the layer situated in the lower part of the zone (A) presenting the topographical difference; (e) and engraving the remaining part of the polysilicon layer as well as the upper electrode layer situated in the lower part.

公开(公告)号：FR2982424A1

公开(公告)日：2013-05-10

申请号：FR1160209

申请日：2011-11-09

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： SAVELLI GUILLAUME ,  CORONEL PHILIPPE ,  GAILLARD FREDERIC ,  MONFRAY STEPHANE

IPC: H01L37/00

Abstract: Système de conversion d'énergie thermique en énergie électrique (S1) destiné à être disposé entre une source chaude (SC) et une source froide (SF) , comportant des moyens de conversion de l'énergie thermique en énergie mécanique (6) et un matériau piézoélectrique, les moyens de conversion de l'énergie thermique en énergie mécanique (6) comportant des groupes (G1, G2 ) de au moins trois bilames (9, 11, 13) reliés mécaniquement entre eux par leur extrémités longitudinales et suspendus au-dessus d'un substrat (12), chaque bilame (9, 11, 13) comportant deux états stables dans lesquels il présente dans chacun des états une courbure, deux bilames directement adjacentes (9, 11, 13) présentant pour une température donnée des courbures opposées, le passage d'un état à stable des bilames (9, 11, 13) à l'autre provoquant la déformation d'un matériau piézoélectrique.

公开(公告)号：FR2860099B1

公开(公告)日：2006-01-06

申请号：FR0310984

申请日：2003-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  CORONEL PHILIPPE ,  HARTMANN JOEL

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786

公开(公告)号：FR2853454B1

公开(公告)日：2005-07-15

申请号：FR0304143

申请日：2003-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MORAND YVES ,  SKOTNICKI THOMAS ,  CERUTTI ROBIN

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A MOS transistor formed in a silicon substrate (101) comprises: (a) an active zone (100) surrounded by an insulating partition (102); (b) a first conducting strip (103) covering a central strip of the active zone; (c) one or more second conducting strips (105, 106, 107) placed in the active zone plumb with the first strip; (d) some conducting regions (108, 109) placed in two cavities in the insulating partition and joined to the ends of the first and second strips; (e) the surfaces of the silicon opposite the strips and conducting regions are covered with an insulator (130) constituting an oxide grid. An independent claim is also included for the production of this MOS transistor.

公开(公告)号：FR2848724B1

公开(公告)日：2005-04-15

申请号：FR0215837

申请日：2002-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

公开(公告)号：FR2860099A1

公开(公告)日：2005-03-25

申请号：FR0310984

申请日：2003-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  CORONEL PHILIPPE ,  HARTMANN JOEL

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L27/11

Abstract: The method involves forming a temporary monocrystalline material portion over a surface (S) of a conducting substrate (100). A semiconductor material (2) is deposited on the portion of temporary material. A part of the temporary material is withdrawn via an access zone. An insulating coating is formed on parts of the material (2). A conducting material (4) is formed above and below a central part of the material (2). An independent claim is also included for a random access memory unit.