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    53.
    发明专利
    未知

    公开(公告)号：DE69732637T2

    公开(公告)日：2005-12-29

    申请号：DE69732637

    申请日：1997-12-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO ,  MAURELLI ALFONSO ,  OLIVO MARCO

    IPC: G06F11/10 ,  G11C29/00 ,  G11C16/06 ,  G11C29/06 ,  G11C29/52

    Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

    56.
    发明专利
    未知

    公开(公告)号：DE69325458T2

    公开(公告)日：1999-10-21

    申请号：DE69325458

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  PADOAN SILVIA

    IPC: G06F1/24 ,  G11C17/00 ,  G11C16/06 ,  G11C16/30

    Abstract: A method for generating a reset signal in an electrically programmable non-volatile storage device (1) of a type which comprises a matrix (2) of memory cells and a control logic portion (3) being supplied a supply voltage (Vcc) and a programming voltage (Vpp), and a threshold detection circuit (5) adapted to detect a decrease in the supply voltage (Vcc), provides for the signal applied to the control logic (3) to be obtained as a change-over function between the output signal from the threshold detector (5) and a reset signal (POR) generated during the power-on transient of the device.

    58.
    发明专利
    未知

    公开(公告)号：DE69325587D1

    公开(公告)日：1999-08-12

    申请号：DE69325587

    申请日：1993-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  MACCARRONE MARCO

    IPC: G11C8/04 ,  G11C16/06 ,  H03K21/00 ,  G11C11/00

    Abstract: A count unit (1) for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter (8) and a number of registers (9, 10) equal in number to the count functions involved. The registers (9, 10) store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter (8) which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One (10) of the registers presents a second parallel input (ADDR) for externally loading an initial data which may be transferred to the other registers (9) via the counter (8).

    59.
    发明专利
    未知

    公开(公告)号：DE69412230D1

    公开(公告)日：1998-09-10

    申请号：DE69412230

    申请日：1994-02-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: A method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with columns of memory elements grouped together to form portions of a bidimensional array of memory elements, the column redundancy circuitry comprising at least one plurality of non-volatile memory registers (RR1-RR4) each one associated to a respective redundancy column of redundancy memory elements and each one programmable to store an address of a defective column and an identifying code (MCS7-MCS10) for identifying the portion of the bidimensional array to which the defective column belongs, provides for supplying each non-volatile memory register (RR1-RR4) with column address signals (CABUS) and with a first subset (R1-R4) of row address signals (RABUS), which when one of the non-volatile memory registers (RR1-RR4) is to be programmed carry the address of a defective column and said identifying code (MCS7-MCS10) respectively, and for activating one signal of a second subset (R5-R8) of the row address signals (RABUS), supplied to programming selection means (6), for selecting one respective non-volatile memory register (RR1-RR4) of said plurality to cause the data carried by the column address signals (CABUS) and by the first subset (R1-R4) of the row address signals to be programmed into said one respective non-volatile memory register (RR1-RR4).

    60.
    发明专利
    未知

    公开(公告)号：DE69222712T2

    公开(公告)日：1998-02-12

    申请号：DE69222712

    申请日：1992-07-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

    Abstract: The discriminating sensitivity of a sense amplifier and the speed of the circuit are increased by exploiting the difference of potential which develops across the output nodes of the two control circuits, employed for enabling/disabling current paths of the input network of the differential amplifier, as a virtual additional signal for the sensing differential amplifier, by employing said output potentials of the two control circuits as virtual reference potentials for the pair of input transistors of the differential amplifier during a discriminating phase of the reading cycle. Two pass-transistors driven by a control signal provide to force to ground potential the output nodes of said control circuits, thus reestablishing a correct ground reference potential of the amplifier, during the final phase of amplification and storage of the extracted datum in an output latch, as well as during the successive standby period. Alternative embodiments also include various anti-overshoot circuits.

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