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    51.
    发明专利
    未知

    公开(公告)号：DE69625327D1

    公开(公告)日：2003-01-23

    申请号：DE69625327

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  FONTANA MARCO ,  BARCELLA ANTONIO

    IPC: G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C7/00

    Abstract: A non-volatile memory device, having the particularity that it comprises an internal bus (3) for the transmission of data and other information of the memory to output pads (4); timer means (8); and means (5, 5') for enabling/disabling access to the internal bus; the timer means (8) time the internal bus to transmit information signals of the memory device that originate from local auxiliary lines (7) over the internal bus (3) when the bus is in an inactive period during a normal memory data reading cycle; the timer means (8) drive the enabling/disabling means (5, 5') to allow/deny access to the internal bus (3) on the part of the information signals or of the data from or to the memory.

    54.
    发明专利
    未知

    公开(公告)号：DE69840370D1

    公开(公告)日：2009-01-29

    申请号：DE69840370

    申请日：1998-02-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C16/20 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10 ,  G11C16/06 ,  G11C16/30

    Abstract: An operating voltage selection circuit for non-volatile semiconductor memories, whose particularity resides in the fact that it comprises: -- means (1) for reading at least one one-time programmable non-volatile memory cell (10), suitable to generate a signal (LV) which indicates the requested type of operating voltage of a non-volatile memory, which depends on the programmed or non-programmed state of the memory cell; -- memory enabling means (5), which comprise an inverter (30, 31) and are provided with means (32) for modifying the switching threshold of the inverter as a function of the signal that indicates the requested type of operating voltage; -- output means (2), which are connected to means for sensing data of the memory and to output terminals of the memory, comprising a CMOS inverter (20, 50) and means (23) for modifying the output current of the inverter as a function of the signal (LV) for indicating the requested type of operating voltage; and -- means (8) for the internal synchronization of the memory, which comprise pluralities of transistors (40, 41, 42) connected in a series/parallel configuration which is determined by the signal (LV) for indicating the requested type of operating voltage, in order to generate signals (CK1, CK2, CK3) for the internal synchronization of the memory.

    56.
    发明专利
    未知

    公开(公告)号：DE60037504T2

    公开(公告)日：2008-12-11

    申请号：DE60037504

    申请日：2000-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: G11C16/28 ,  G11C11/56

    Abstract: The invention relates to a circuit structure (1) for reading data contained in an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix (2) of memory cells (3) and at least one reference cell (4) for comparison with a memory cell (3) during a reading phase. The reference cell (4) is incorporated in a reference cells sub-matrix (5) which is structurally independent of the matrix (2) of memory cells (3). Also provided is a conduction path between the matrix (2) and the sub-matrix (5), which path includes bit lines (b1ref) of the submatrix (5) of reference cells (4) extended continuously into the matrix (2) of memory cells (3)

    59.
    发明专利
    未知

    公开(公告)号：DE69726136T2

    公开(公告)日：2004-08-26

    申请号：DE69726136

    申请日：1997-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  GASTALDI ROBERTO ,  CALLIGARO CRISTIANO

    IPC: G11C11/56 ,  G11C16/08 ,  G11C16/30 ,  G11C11/00 ,  G11C16/06

    Abstract: The present invention relates to a circuit for generating a regulated voltage (RV), in particular for gate terminals of non-volatile memory cells of the floating gate type, which comprises a generator circuit (OSC,CHP) adapted to generate an unregulated voltage (VCHP) on its output, a comparator circuit coupled to the output of the generator circuit (OSC,CHP), including a reference element consisting of a non-volatile memory cell (REFC) of the floating gate type and adapted to output an electric error signal (ID) tied to the difference between the unregulated voltage (VCHP) and the threshold voltage of the cell (REFC), and a regulator circuit (CSEL,CBIAS,IVC,DRV,TR) coupled to the output of the comparator circuit and operative to regulate the unregulated voltage (VCHP) based on the value of the electric error signal (ID). Through the present circuit, the regulated voltage (RV) is made programmable and tied to the parameters of the memory cell (REFC).

    60.
    发明专利
    未知

    公开(公告)号：DE69627318T2

    公开(公告)日：2004-02-12

    申请号：DE69627318

    申请日：1996-08-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  CALLIGARIO CRISTIANO ,  MANSTRETTA ALESSANDRO ,  TORELLI GUIDO

    IPC: G11C16/02 ,  G11C11/56 ,  G11C11/00

    Abstract: In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input (RADR,CADR), each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.

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