中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

92 records (took 0.026 seconds)

    Level shifter for semiconductor memory device implemented with low-voltage transistors
    51.
    发明公开
    Level shifter for semiconductor memory device implemented with low-voltage transistors 有权
    Mit Niederspannungstransistoren实施者Pegelschieberfüreine Halbleiterspeichervorrichtung

    公开(公告)号：EP1835507A1

    公开(公告)日：2007-09-19

    申请号：EP06111337.9

    申请日：2006-03-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C8/08 ,  G11C16/12 ,  G11C16/08 ,  G11C7/10 ,  H03K19/0185 ,  H03K3/356

    CPC classification number: G11C5/145 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H03K3/356113

    Abstract: A level shifter (135') is proposed. The level shifter includes a stage having a first branch (M1, M3, M5) and a second branch (M2, M4, M6), each branch including: a selection terminal for receiving a selection signal (Vp) , the selection signal received by the first branch and the second branch being alternatively at a first voltage (GND) and at a second voltage (Vdd) higher than the first voltage in absolute value, a service terminal for receiving a third voltage (POSV1) higher than the second voltage in absolute value, an input circuit ( 305) for coupling an intermediate node (IN1, IN2) to the selection terminal when at the second voltage or for insulating the intermediate node from the selection terminal otherwise, an interface circuit (310) for coupling an output terminal (OUTI, OUT2) to the intermediate node when coupled or for insulating the output terminal from the intermediate node otherwise, and an output circuit (315) for insulating the service terminal from the output terminal when coupled or for coupling the service terminal to the output terminal otherwise, the output terminals of the first branch and the second branch providing an output signal being alternatively at the second voltage or at the third voltage according to the selection signal.

    Abstract translation: 提出了一种电平移位器（135'）。 电平移位器包括具有第一分支（M1，M3，M5）和第二分支（M2，M4，M6）的级，每个分支包括：用于接收选择信号（Vp）的选择端，由 第一分支和第二分支交替地以比绝对值的第一电压高的第一电压（GND）和第二电压（Vdd），用于接收比第二电压高的绝对值的第三电压（POSV1） 绝对值，用于当处于第二电压时将中间节点（IN1，IN2）耦合到选择端子或用于将中间节点与选择终端绝缘的输入电路（305），否则，用于耦合输出的接口电路（310） 当输出端子与中间节点耦合或绝缘时，终端（OUTI，OUT2）到中间节点，否则输出端子（OUTI，OUT2）和用于将服务终端与输出端子隔离的输出电路（315） 服务终端到输出端子，否则，第一分支和第二分支的输出端子根据选择信号提供交替地处于第二电压或第三电压的输出信号。

    A method for sector erasure and sector erase verification in a non-voltaile FLASH EEPROM
    56.
    发明公开
    A method for sector erasure and sector erase verification in a non-voltaile FLASH EEPROM 审中-公开
    一种用于扇区擦除方法和擦除验证非易失性闪存EEPROM存储器

    公开(公告)号：EP1265252A1

    公开(公告)日：2002-12-11

    申请号：EP01830369.3

    申请日：2001-06-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Scommegna, Salvatrice

    IPC: G11C16/34

    CPC classification number: G11C16/344 ,  G11C16/3436

    Abstract: Described herein is an erasure method for an electrically erasable nonvolatile memory device (1), in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array (3) formed by a plurality of memory cells (8) arranged in rows and columns and grouped in sectors (4) each formed by a plurality of subsectors (6), which are in turn formed by one or more rows. Erasure of the memory array (3) is performed by sectors and for each sector (4) envisages applying an erasure pulse to the gate terminals of all the memory cells (8) of the sector (4), verifying erasure of the memory cells (8) of each subsector (6), and applying a further erasure pulse to the gate terminals of the memory cells (8) of only the subsectors (6) not completely erased.

    Abstract translation: 在所描述的是用于向电可擦除非易失性存储器设备（1），尤其是EEPROM-FLASH非易失性存储器件的擦除方法，其包括存储器阵列（3）通过（8）布置成行和列的存储单元的多个形成 在扇区分组（4），每个由子行业的多个形成，（6），其又通过一个或多个列构成。 存储器阵列（3）的擦除执行通过扇区和每个扇区（4）设想适用于擦除脉冲到所有的存储单元的栅极端子（8）的扇区（4）的验证的存储器单元的擦除（ 8）每个分部门（6），以及将另外的擦除脉冲施加到存储单元的栅极端子（8）仅分部门（6）未完全呼叫擦除。

    Memory device having improved yield and reliability
    57.
    发明授权
    Memory device having improved yield and reliability 失效
    具有改进的可靠性和改进的结果存储装置

    公开(公告)号：EP0766174B1

    公开(公告)日：2002-05-22

    申请号：EP95830408.1

    申请日：1995-09-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Branchetti, Maurizio ,  Golla, Carla ,  Campardo, Giovanni

    IPC: G06F11/10

    CPC classification number: G06F11/1008

    Abstract: The present invention relates to a memory device of the type comprising: at least one first (M1) and one second (M2) memory cell array for storage respectively of a first plurality of user data and a second plurality of error identification and correction data, first (D1) and second (D2) decoding means connected respectively to the first (M1) and second (M2) memory cell array for selection and reading respectively of the first and second pluralities of data, error identification means (L1) coupled to said first (D1) and second (D2) decoder means, and error correction means (C1,C2,EN) operationally connected to said first (D1) and second (D2) decoder means and to said error identification means (L1), and characterized in that it comprises at least one logical control unit (L2) operationally connected to the second decoder means (D2), to error identification means (L1) and to the error correction means (C1,C2,EN) to enable said second decoder means (D2) and said error correction means (C1,C2,EN) if an error is detected by the error identification means (L1).

    Method for storing and reading data in a multibit nonvolatile memory with a non-binary number of bits per cell
    58.
    发明公开
    Method for storing and reading data in a multibit nonvolatile memory with a non-binary number of bits per cell 有权
    与非二进制数每单元的比特存储和读取的非易失性Multibitspeichers的数据的方法

    公开(公告)号：EP1199725A1

    公开(公告)日：2002-04-24

    申请号：EP00830671.4

    申请日：2000-10-13

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C11/56 ,  G11C8/00

    CPC classification number: G11C11/5642 ,  G11C8/00 ,  G11C11/56 ,  G11C11/5621

    Abstract: The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a non-binary number of bits, for example three. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in a same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading, in a same clock cycle, the stored data word.

    Abstract translation: 的数据管理方法适用于具有由存储单元形成的多个存储器阵列中的多级非易失性存储器设备。 每一个存储单元的存储位的非二进制数，例如三个。 以这种方式，一个字节的数据存储在存储器单元的非整数。 所述管理方法包括存储，在相同的时钟周期中，由一个字节形成的多个数据字，通过编程的相邻存储器单元的预设数目。 读书是执行了由同一个时钟周期，存储的数据字读。

Patent Agency Ranking