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    Charge pump circuit
    53.
    发明公开
    Charge pump circuit 审中-公开
    Ladungspumpenschaltung

    公开(公告)号：EP1791245A1

    公开(公告)日：2007-05-30

    申请号：EP05111284.5

    申请日：2005-11-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: H02M3/07

    CPC classification number: H02M3/073

    Abstract: A charge pump circuit comprises at least one pump stage. Said pump stage includes a capacitor (C1,C2,C3;C'1,C'2,C'3) having a first plate and a second plate. The pump stage further includes a first circuital node (N1,N3,N5;N'2,N'4,N'6) connected to the first plate, a voltage of the first circuital node is forced to a first forced voltage (GND) during a forcing phase of the charge pump operation, and a second circuital node (N2,N4,N6;N'1,N'3,N'5) connected to the second plate, a voltage of the second circuital node is forced to a second forced voltage (Vdd) during the forcing phase. The voltages of the first and the second circuital nodes are free of changing with respect to the first and to the second forced voltage, respectively, except during said forcing phase. The pump stage still further includes a first forcing circuit (110,130,150;420,440,460) associated to the first circuital node, the first forcing circuit being activable for forcing the voltage of the first circuital node to the first forced voltage during the forcing phase, and a second forcing circuit (120,140,160;410,430,450) associated to the second circuital node, the second forcing circuit being activable for forcing the voltage of the second circuital node to the second forced voltage during the forcing phase.

    Abstract translation: 电荷泵电路包括至少一个泵级。 所述泵级包括具有第一板和第二板的电容器（C1，C2，C3; C'1，C'2，C'3）。 泵级还包括连接到第一板的第一电路节点（N1，N3，N5; N'2，N'4，N'6），第一电路节点的电压被强制为第一强制电压（GND ）和连接到第二板的第二电路节点（N2，N4，N6; N'1，N'3，N'5），第二电路节点的电压被强制 在强制阶段到第二强制电压（Vdd）。 除了在所述强制阶段之外，第一和第二电路节点的电压分别相对于第一和第二强制电压没有变化。 所述泵级还包括与所述第一电路节点相关联的第一强制电路（110,130,150; 420,440,460），所述第一强制电路可激活以在所述强制阶段迫使所述第一电路节点的电压达到所述第一强制电压;以及第二强制电路 与所述第二电路节点相关联的所述第二强制电路（120,140,​​160; 410,430,450），所述第二强制电路是可激活的，以在所述强制阶段期间迫使所述第二电路节点的电压达到所述第二强制电压。

    NAND flash memory with erase verify based on shorter delay before sensing
    55.
    发明公开
    NAND flash memory with erase verify based on shorter delay before sensing 有权
    NAND闪存擦除验证基于传感之前更短的延迟

    公开(公告)号：EP1752989A1

    公开(公告)日：2007-02-14

    申请号：EP05106976.3

    申请日：2005-07-28

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Bovino, Angelo ,  Micheloni, Rino ,  Ravasio, Roberto

    IPC: G11C16/32 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/32 ,  G11C16/344

    Abstract: A non-volatile memory device (100) is proposed. The non-volatile memory device includes a plurality of memory cells (110) each one having a programmable threshold voltage, and means for reading (130, 140, 150) a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging (Pc) a reading node (BL) associated with the selected memory cell with a charging voltage (Vc), means for biasing (130) the selected memory cell with a biasing voltage, means for connecting (120d, 120s) the charged reading node with the biased selected memory cell, and means for sensing (205) a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages (V R ) the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay (Te), wherein for at least a second one of the reference voltages (Vga) the biasing voltage is a second biasing voltage (V R ) different from the second reference voltage, and the delay is a second delay (Teg) different from the first delay.

    Abstract translation: 一种非易失性存储器设备（100）提议。 非易失性存储器设备包括存储器单元的多个（110）每一个具有可编程阈值电压的装置，以及用于读出（130，140，150）相对于一组选定的存储器单元内的基准电压复数，用于 每个所选择的存储单元中的装置，用于读取包括用于充电（PC）读出节点（BL）用的充电电压所选择的存储器单元相关联（VC），用于偏置（130）所述选定存储器单元与偏置电压， 装置，用于连接（120D，120秒）与该偏置的选定存储器单元中的电荷的读出节点的装置，以及用于感测（205）在从所述连接的预定义的延迟之后读出节点的电压，对于参考电压中的至少一个第一个 （VR）的偏置电压是一个第一偏置电压等于所述第一基准电压和所述延迟是共同的第一延迟（TE），worin对于参考电压中的至少一个第二个（VGA）的偏置电压是一个第二偏置 电压 （V R）从所述第二参考电压不同，并且延迟为第二延迟（TEG）与所述第一延迟不同。

    Multistage regulator for charge-pump boosted voltage applications
    56.
    发明公开
    Multistage regulator for charge-pump boosted voltage applications 有权
    MehrstufenreglerfürLadungspumpen在Spannungserhöhungsanwendungen

    公开(公告)号：EP1750271A1

    公开(公告)日：2007-02-07

    申请号：EP05425558.3

    申请日：2005-07-28

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Crippa, Luca ,  Sangalli, Miriam ,  Ragone, Giancarlo ,  Micheloni, Rino

    IPC: G11C5/14 ,  G11C16/30

    CPC classification number: G11C5/145 ,  G11C16/30

    Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance (C LOAD ) of an integrated device at a certain charge-pump generated boosted voltage is safely implemented without obliging to integrate high voltage transistor structures of type of conductivity of the same sign of the boosted voltage (high-side transistors).
    Another fulfilled objective is to provide a multilevel nonvolatile flash memory device comprising a boosted voltage regulator that can be entirely fabricated with a low cost nonvolatile flash memory fabrication process.
    Basically, the multistage circuit for regulating the charge voltage or the discharge current of a capacitance in an integrated device, comprising at least a first stage and an output stage in cascade to the first stage and coupled to the capacitance, has the first stage supplied at an unboosted power supply voltage (V DD ) of the integrated device and the output stage supplied at an unregulated charge-pump generated boosted voltage (V PUMP ) and is composed of a transistor (M NOUT ) of type of conductivity opposite to the sign of the boosted voltage and of the power supply voltage.
    The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up (R PULL-UP ) or a voltage limiter.

    Abstract translation: 在一定的电荷泵产生的升压电压下，用于调节集成器件的电容（C LOAD）的充电电压或放电电流的多级电路被安全地实现，而不必集成将相同电导率的高电压晶体管结构 升压电压（高侧晶体管）的符号。 另一个实现的目标是提供一种多级非易失性闪存器件，其包括可以用低成本的非易失性闪速存储器制造工艺完全制造的升压型稳压器。 基本上，用于调节集成装置中的电容的充电电压或放电电流的多级电路包括至少第一级和级联到第一级并耦合到电容的输出级，第一级提供在 该集成装置的未升压的电源电压（V DD）和在未调节的电荷泵产生的升压电压（V PUMP）下提供的输出级，并且由一个导体类型的晶体管（M NOUT）构成， 升压电压和电源电压。 输出级晶体管的漏极通过电阻上拉（R PULL-UP）或限压器耦合到升压电压。

    Memory with embedded error correction code circuit
    60.
    发明公开
    Memory with embedded error correction code circuit 有权
    Fehlerkorrekturkode-Einrichtung的Speicher mit eingebauter

    公开(公告)号：EP1635261A1

    公开(公告)日：2006-03-15

    申请号：EP04425678.2

    申请日：2004-09-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Bovino, Angelo ,  Altieri, Vincenzo

    IPC: G06F11/10

    CPC classification number: G06F11/1048

    Abstract: A memory (104) has one bus (112) for data, addresses, and commands. A data register (114) is coupled to the bus (112) to store the data written to and read from the memory (104), a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code (ECC) circuit for calculating an ECC. The memory (104) is configured (168, 200, 206, 237) to be responsive to external commands for controlling the operation of the ECC circuit (140) for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

    Abstract translation: 存储器（104）具有用于数据，地址和命令的一个总线（112）。 数据寄存器（114）耦合到总线（112）以存储写入存储器（104）和从存储器（104）读取的数据，命令寄存器耦合到总线以接收存储器命令，并且地址寄存器耦合到 总线来解决内存。 存储器还包括用于计算ECC的纠错码（ECC）电路。 存储器（104）被配置为响应于用于控制ECC电路（140）的操作的外部命令，用于读取或写入与控制读取或写入的外部命令分离的ECC 的内存数据。 存储器还可以包括状态寄存器，其存储关于ECC的通过或失败的信息。

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