Abstract:
Integrated transistor device (10) formed in a chip of semiconductor material (15) having an electrical-insulation region (31) delimiting an active area (30) accommodating a bipolar transistor (11) of vertical type and a MOSFET (12) of planar type, contiguous to one another. The active area accommodates a collector region (18); a bipolar base region (19) contiguous to the collector region; an emitter region (20) within the bipolar base region; a source region (23), arranged at a distance from the bipolar base region; a drain region (24); a channel region (22) arranged between the source region and the drain region; and a well region (35). The drain region (24) and the bipolar base region (19) are contiguous and form a common base structure (19, 24, 37) shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device (10) has a high input impedance and is capable of driving high currents, while only requiring a small integration area.
Abstract:
In a nonvolatile memory device, data stored in a memory cell (21a, 21b) are associated to whether or not the memory cell is switchable between a first state and a second state. Memory cells are irreversibly programmed by applying an irreversible programming signal (I IRP ), such that the nonvolatile memory cells (21a) are made not switchable between the first state and the second state in response to the irreversible programming signal (I IRP ). Reading memory cells includes: assessing (100, 110, 120, 140, 150, 160) whether a memory cell (21a, 21b) is switchable between a first state and a second state; determining that a first irreversible logic value ("1") is associated to the memory cell (21a), if the memory cell (21a) is not switchable between the first state and the second state (130); and determining that a second irreversible logic value ("0") is associated to the memory cell (21b), if the memory cell (21b) is switchable between the first state and the second state (170).
Abstract:
Phase-change memory cell (61), formed by a phase-change memory element (64) and by a selection element (65), which is formed in a semiconductor material body (20) and is connected to the phase-change memory element (64). The phase-change memory element (64) is made up of a chalcogenic material layer (17) and a heater (63). The selection element (65) is in direct contact with the heater (63) and extends through a dielectric region (38,24) arranged on top of and contiguous to the semiconductor material body (20). A dielectric material layer (32) is arranged on the dielectric region (24) and houses a portion of the chalcogenic material layer (17).
Abstract:
A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.
Abstract:
A memory cell (2) includes a memory element (3) and a selection element (30) coupled to said memory element (3). The selection element (30) includes a first junction portion (128a), having a first type of conductivity, and a second junction portion (128b), having a second type of conductivity and forming a rectifying junction (38) with the first junction portion (128a). The first junction portion (128a) and the second junction portion (128b) are made of materials selected in the group consisting of: chalcogenides and conducting polymers.
Abstract:
The present invention proposes a Field Programmable Gate Array (FPGA) device (100) comprising a plurality of configurable electrical connections (115 1 -115 2 ,115 1 -115 3 ), a plurality of controlled switches (205), each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit (125) including an arrangement of a plurality of control cells (200). Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element (210,215) adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element (P1;F1) coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.