公开(公告)号：EP1791181A1

公开(公告)日：2007-05-30

申请号：EP05425835.5

申请日：2005-11-25

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Cappelletti, Paolo Giuseppe

IPC: H01L27/07 ,  H01L21/8249 ,  H01L27/24

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L21/8249 ,  H01L27/0705

Abstract: Integrated transistor device (10) formed in a chip of semiconductor material (15) having an electrical-insulation region (31) delimiting an active area (30) accommodating a bipolar transistor (11) of vertical type and a MOSFET (12) of planar type, contiguous to one another. The active area accommodates a collector region (18); a bipolar base region (19) contiguous to the collector region; an emitter region (20) within the bipolar base region; a source region (23), arranged at a distance from the bipolar base region; a drain region (24); a channel region (22) arranged between the source region and the drain region; and a well region (35). The drain region (24) and the bipolar base region (19) are contiguous and form a common base structure (19, 24, 37) shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device (10) has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

Abstract translation: 在具有电绝缘区（31），在有源区（30）限定容纳垂直型的平面的一个双极型晶体管（11）和一个MOSFET（12）的半导体材料的芯片（15）上综合晶体管装置（10） 型，邻接彼此。 有源区可容纳的集电极区域（18）; 双极基极区域（19）邻接所述集电极区; 到发射极双极基极区域内的区域（20）; 一个源极区（23），在从双极基极区域的距离布置; 漏极区（24）; 源区和漏区之间设置的沟道区（22）; 和一个阱区（35）。 漏极区（24）和双极基极区域（19）是连续的，并形成由双极晶体管和MOSFET共有的共有底边结构（19，24，37）。 由此，集成晶体管装置（10）具有高输入阻抗和能够驱动大电流，同时仅需要一个小的积分区。

公开(公告)号：EP2045814A1

公开(公告)日：2009-04-08

申请号：EP07425616.5

申请日：2007-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio

IPC: G11C16/02 ,  G11C16/10 ,  G11C17/14 ,  G11C16/26

CPC classification number: G11C13/0069 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0078

Abstract: In a nonvolatile memory device, data stored in a memory cell (21a, 21b) are associated to whether or not the memory cell is switchable between a first state and a second state. Memory cells are irreversibly programmed by applying an irreversible programming signal (I IRP ), such that the nonvolatile memory cells (21a) are made not switchable between the first state and the second state in response to the irreversible programming signal (I IRP ). Reading memory cells includes: assessing (100, 110, 120, 140, 150, 160) whether a memory cell (21a, 21b) is switchable between a first state and a second state; determining that a first irreversible logic value ("1") is associated to the memory cell (21a), if the memory cell (21a) is not switchable between the first state and the second state (130); and determining that a second irreversible logic value ("0") is associated to the memory cell (21b), if the memory cell (21b) is switchable between the first state and the second state (170).

Abstract translation: 在非易失性存储器装置中，存储在存储器单元中的数据（21A，21B）被关联到所述存储器单元是否为第一状态和第二状态之间切换。 存储单元通过施加不可逆编程信号（I IRP）不可逆编程，检查做了非易失性存储单元（21a）的由响应于不可逆编程信号（I IRP）的第一状态和所述第二状态之间不切换。 读取存储器单元包括：评估（100，110，120，140，150，160）是否存储单元（21A，21B）为第一状态和第二状态之间切换; 确定性挖掘做了第一不可逆逻辑值（“1”）关联到所述存储单元（21a），如果存储单元（21a）没有所述第一状态和所述第二状态（130）之间切换; 和确定性挖掘做了第二不可逆逻辑值（“0”）被关联到所述存储单元（21B），如果存储单元（21B）是在第一状态和第二状态（170）之间切换。

公开(公告)号：EP1326254B1

公开(公告)日：2009-02-25

申请号：EP01830806.4

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Bosisio, Giorgio ,  Pellizzer, Fabio

IPC: G11C11/34

CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

公开(公告)号：EP1845567A1

公开(公告)日：2007-10-17

申请号：EP06425257.0

申请日：2006-04-11

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Ottogalli, Federica

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase-change memory cell (61), formed by a phase-change memory element (64) and by a selection element (65), which is formed in a semiconductor material body (20) and is connected to the phase-change memory element (64). The phase-change memory element (64) is made up of a chalcogenic material layer (17) and a heater (63). The selection element (65) is in direct contact with the heater (63) and extends through a dielectric region (38,24) arranged on top of and contiguous to the semiconductor material body (20). A dielectric material layer (32) is arranged on the dielectric region (24) and houses a portion of the chalcogenic material layer (17).

Abstract translation: 由相变存储元件（64）和选择元件（65）形成的相变存储单元（61），其形成在半导体材料体（20）中，并连接到相变存储元件 （64）。 相变存储元件（64）由硫属材料层（17）和加热器（63）构成。 选择元件（65）与加热器（63）直接接触并且延伸穿过布置在半导体材料体（20）顶部并邻近半导体材料体（20）的电介质区域（38,24）。 介电材料层（32）布置在电介质区域（24）上并容纳一部分硫属材料层（17）。

公开(公告)号：EP1489622B1

公开(公告)日：2007-08-15

申请号：EP03425390.6

申请日：2003-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Casagrande, Giulio

IPC: G11C11/34

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

公开(公告)号：EP1729355A1

公开(公告)日：2006-12-06

申请号：EP05104879.1

申请日：2005-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Varesi, Enrico ,  Pirovano, Agostino ,  Petruzza, Pietro

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.

Abstract translation: 用于制造相变存储单元的方法包括在半导体晶片（10）中形成加热元件（25a）和在与加热器元件（25a）接触并与之接触的相变材料的存储区域（31a）的步骤。 为了形成加热器元件（25a）和相变储存区域（31a），首先形成加热器结构，并且相变层（31）沉积在加热器结构上并与加热器结构接触。 然后，通过随后的自对准蚀刻步骤限定相变层（31）和加热器结构。

公开(公告)号：EP1675183A1

公开(公告)日：2006-06-28

申请号：EP04425931.5

申请日：2004-12-21

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Pirovano, Agostino

IPC: H01L27/24

CPC classification number: H01L27/2409 ,  G11C13/0016 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory cell (2) includes a memory element (3) and a selection element (30) coupled to said memory element (3). The selection element (30) includes a first junction portion (128a), having a first type of conductivity, and a second junction portion (128b), having a second type of conductivity and forming a rectifying junction (38) with the first junction portion (128a). The first junction portion (128a) and the second junction portion (128b) are made of materials selected in the group consisting of: chalcogenides and conducting polymers.

Abstract translation: 存储单元（2）包括存储元件（3）和耦合到所述存储元件（3）的选择元件（30）。 选择元件（30）包括具有第一类型导电性的第一接合部分（128a）和具有第二类型导电性的第二接合部分（128b），并且与第一接合部分形成整流接头（38） （128A）。 第一接合部分（128a）和第二接合部分（128b）由选自以下的材料制成：硫族化物和导电聚合物。

公开(公告)号：EP1519489A1

公开(公告)日：2005-03-30

申请号：EP03021455.5

申请日：2003-09-23

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  De Sandre, Guido ,  Bez, Roberto

IPC: H03K19/177

CPC classification number: G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

Abstract: The present invention proposes a Field Programmable Gate Array (FPGA) device (100) comprising a plurality of configurable electrical connections (115 1 -115 2 ,115 1 -115 3 ), a plurality of controlled switches (205), each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit (125) including an arrangement of a plurality of control cells (200). Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element (210,215) adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element (P1;F1) coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

Abstract translation: 本发明提出了一种包括多个可配置电连接（1151-1152,1151-1153）的现场可编程门阵列（FPGA）装置，多个受控开关（205），每个控制开关适于启动/ 响应于开关控制信号激活至少一个相应的电连接，以及包括多个控制单元（200）的布置的控制单元（125）。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件（210,215），其适于以易失性方式存储对应于至少一个 控制开关，并且向控制开关提供与存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件（P1; F1），非易失性存储元件适于以非易失性方式存储控制逻辑值。