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    전계 방출 소자의 캐소드 팁 제조 방법
    51.
    发明授权
    전계 방출 소자의 캐소드 팁 제조 방법 失效
    场发射装置的阴极提示制作方法

    公开(公告)号：KR100250458B1

    公开(公告)日：2000-04-01

    申请号：KR1019970058524

    申请日：1997-11-06

    Applicant: 한국전자통신연구원

    Inventor： 송윤호 ,  조경익 ,  이진호

    IPC: H01J1/304 ,  H01J9/02

    CPC classification number: H01J9/025 ,  H01J2201/30411 ,  H01J2209/0226 ,  H01J2237/06341 ,  H01J2329/0415

    Abstract: PURPOSE: A method for manufacturing a cathode tip of a field emission device is provided to manufacture a stable and even cathode tip in the low temperature by using a selective etching method of a silicon layer, in which ion is injected. CONSTITUTION: In a method for manufacturing a cathode tip of a field emission device, an insulating board(21), a conductive layer(22), a silicon layer(23B) and a cathode tip(25) are included. The conductive layer(22) and the silicon layer(23B) are layed on the insulating board(21) in order. In the insulating board(21), an oxide, a nitride film, quartz and a glass are used. In conductive layer(22), a metal and a silicon, in which ion is injected, are used. The cathode tip(25) of the sharp cone type is gained by removing a silicon layer with wet etching. In wet etching, HF, CH3COOH and HNO3 are used with being mixed. The solution has the high etching ratio about the silicon layer, in which ion is injected, but it has the low etching ration about the silicon(23B), on which doping isn't carried out, so the clear cathode tip(25) is manufactured.

    Abstract translation: 目的：提供一种用于制造场致发射器件的阴极尖端的方法，通过使用其中注入离子的硅层的选择性蚀刻方法在低温下制造稳定且均匀的阴极尖端。 构成：在场致发射器件的阴极尖端的制造方法中，包括绝缘板（21），导电层（22），硅层（23B）和阴极端（25）。 导电层（22）和硅层（23B）依次铺设在绝缘板（21）上。 在绝缘板（21）中，使用氧化物，氮化物膜，石英和玻璃。 在导电层（22）中，使用注入离子的金属和硅。 尖锐锥形的阴极尖端（25）通过用湿蚀刻去除硅层来获得。 在湿蚀刻中，混合使用HF，CH 3 COOH和HNO 3。 该解决方案具有高的蚀刻率，其中注入了离子，但是对于不进行掺杂的硅（23B），其蚀刻比率低，所以透明阴极尖端（25）为 制造。

    SELF-ALIGNED GATED EMITTER TIP ARRAYS
    54.
    发明申请
    SELF-ALIGNED GATED EMITTER TIP ARRAYS 审中-公开
    自对准浇口发射器提升阵列

    公开(公告)号：US20160254114A1

    公开(公告)日：2016-09-01

    申请号：US14935993

    申请日：2015-11-09

    Applicant: Massachusetts Institute of Technology

    Inventor： Arash Akhavan Fomani ,  Luis Fernando Velasquez-Garcia ,  Akintunde I. Akinwande

    IPC: H01J9/02 ,  H01J1/304

    CPC classification number: H01J9/025 ,  H01J1/304 ,  H01J2201/30411 ,  H01L21/00 ,  H01T19/04 ,  H01T23/00

    Abstract: Methods for fabrication of self-aligned gated tip arrays are described. The methods are performed on a multilayer structure that includes a substrate, an intermediate layer that includes a dielectric material disposed over at least a portion of the substrate, and at least one gate electrode layer disposed over at least a portion of the intermediate layer. The method includes forming a via through at least a portion of the at least one gate electrode layer. The via through the at least one gate electrode layer defines a gate aperture. The method also includes etching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure.

    Abstract translation: 描述了自对准浇口尖端阵列的制造方法。 该方法在包括衬底，包括设置在衬底的至少一部分上的电介质材料的中间层以及设置在中间层的至少一部分上的至少一个栅电极层的多层结构上进行。 该方法包括通过至少一个栅极电极层的至少一部分形成通孔。 通过至少一个栅极电极层的通孔限定栅极孔径。 该方法还包括蚀刻靠近栅极孔的中间层的至少一部分，使得在多层结构中形成至少部分被沟槽包围的发射极结构。

    Ion source with cathode having an array of nano-sized projections
    56.
    发明授权
    Ion source with cathode having an array of nano-sized projections 有权
    具有阴极的离子源具有纳米尺寸的突起阵列

    公开(公告)号：US08866068B2

    公开(公告)日：2014-10-21

    申请号：US13728950

    申请日：2012-12-27

    Applicant: Schlumberger Technology Corporation

    Inventor： Jani Reijonen ,  Luke Perkins ,  Harold Pfutzner

    IPC: G01V5/00 ,  H01J27/20 ,  G01V5/08

    CPC classification number: H01J27/205 ,  G01V5/085 ,  H01J1/3044 ,  H01J3/04 ,  H01J2201/30411

    Abstract: An ion source for use in a particle accelerator includes at least one cathode. The at least one cathode has an array of nano-sized projections and an array of gates adjacent the array of nano-sized projections. The array of nano-sized projections and the array of gates have a first voltage difference such that an electric field in the cathode causes electrons to be emitted from the array of nano-sized projections and accelerated downstream. There is a ion source electrode downstream of the at least one cathode, and the at least one cathode and the ion source electrode have the same voltage applied such that the electrons enter the space encompassed by the ion source electrode, some of the electrons as they travel within the ion source electrode striking an ionizable gas to create ions.

    Abstract translation: 用于粒子加速器的离子源包括至少一个阴极。 所述至少一个阴极具有纳米尺寸突起的阵列和邻近纳米尺寸突起阵列的门阵列。 纳米尺寸突起阵列和栅极阵列具有第一电压差，使得阴极中的电场使电子从纳米尺寸突起阵列发射并加速下游。 在至少一个阴极的下游存在离子源电极，并且至少一个阴极和离子源电极施加相同的电压，使得电子进入由离子源电极包围的空间中，一些电子就像它们 在离子源电极内行进进入可电离气体以产生离子。

    CONDUCTIVE NANOSTRUCTURE, METHOD FOR MOLDING SAME, AND METHOD FOR MANUFACTURING A FIELD EMITTER USING SAME
    58.
    发明申请
    CONDUCTIVE NANOSTRUCTURE, METHOD FOR MOLDING SAME, AND METHOD FOR MANUFACTURING A FIELD EMITTER USING SAME 有权
    导电性纳米结构，其成型方法以及使用其制造场致发射体的方法

    公开(公告)号：US20130134860A1

    公开(公告)日：2013-05-30

    申请号：US13704902

    申请日：2011-02-23

    Applicant: Yong Hyup Kim ,  Wal Jun Kim

    Inventor： Yong Hyup Kim ,  Wal Jun Kim

    IPC: H01J9/02 ,  H01J1/304 ,  B23H9/00

    CPC classification number: H01J9/025 ,  B23H9/00 ,  H01B1/04 ,  H01B1/08 ,  H01J1/304 ,  H01J1/3044 ,  H01J2201/30411 ,  H01J2201/30434 ,  H01J2201/30449 ,  H01J2201/30469

    Abstract: The present invention relates to a conductive nanostructure, a method for molding the same, and a method for manufacturing a field emitter using the same. More particularly, the present invention relates to a field-emitting nanostructure comprising a conductive substrate, a conductive nanostructure arranged on the conductive substrate, and a conductive interfacial compound disposed in the interface between the conductive substrate and the conductive nanostructure, as well as to a method for molding the same, and a method for manufacturing a field emitter using the same.

    Abstract translation: 导电纳米结构体及其成型方法技术领域本发明涉及导电性纳米结构体，其成型方法及使用其的场致发射体的制造方法。 更具体地说，本发明涉及一种场致发射纳米结构，其包括导电衬底，布置在导电衬底上的导电纳米结构以及布置在导电衬底和导电纳米结构之间的界面中的导电界面化合物，以及一 其制造方法以及使用该场致发射体的制造方法。

    High pressure field emitter, photoionization, plasma initiation and field devices
    59.
    发明授权
    High pressure field emitter, photoionization, plasma initiation and field devices 失效
    高压场发射器，光电离，等离子体引发和现场设备

    公开(公告)号：US08312704B2

    公开(公告)日：2012-11-20

    申请号：US11383847

    申请日：2006-05-17

    Applicant: John Patrick Keady

    Inventor： John Patrick Keady

    IPC: F03H1/00

    CPC classification number: F03H1/0081 ,  F03H1/0012 ,  H01J27/26 ,  H01J2201/30411 ,  H01S5/105

    Abstract: At least one exemplary embodiment is directed to a propulsion device that ionizes a portion of a medium and ExB drifts the ionized portion providing thrust where the ionized portion is created using high pressure field emitters comprising: a substrate layer; a gate layer; a field emitter tip; and a cover layer, wherein the field emitter tip is configured to emit electrons in a region when there is a potential difference between the gate layer and the field emitter tip, where the cover layer separates an ambient environment at a pressure from the region, and where a substantial portion of the electrons pass through the cover layer.

    Abstract translation: 至少一个示例性实施例涉及一种电离介质的一部分的推进装置，并且ExB使用高压场发射器漂移产生离子化部分的离子化部分的离子化部分，其包括：基底层; 门层; 场发射器尖端; 以及覆盖层，其中所述场发射极尖端被配置为在所述栅极层和所述场致发射极尖端之间存在电位差的区域中发射电子，其中所述覆盖层在与所述区域的压力下分离周围环境，以及 其中大部分电子通过覆盖层。

    METHOD FOR PRODUCING A FIELD-EMITTER ARRAY WITH CONTROLLED APEX SHARPNESS
    60.
    发明申请
    METHOD FOR PRODUCING A FIELD-EMITTER ARRAY WITH CONTROLLED APEX SHARPNESS 有权
    用于生产具有受控APEX锐度的场发射阵列的方法

    公开(公告)号：US20110104832A1

    公开(公告)日：2011-05-05

    申请号：US13001449

    申请日：2009-05-29

    Applicant: Eugenie Kirk ,  Soichiro Tsujino

    Inventor： Eugenie Kirk ,  Soichiro Tsujino

    IPC: H01L21/30

    CPC classification number: H01J9/025 ,  H01J1/3044 ,  H01J2201/30411 ,  H01J2209/0223

    Abstract: A method of manufacturing field-emitter arrays by a molding technique includes uniformly controlling a shape of mold holes to obtain field emitter tips having diameters below 100 nm and blunted side edges. Repeated oxidation and etching of a mold substrate formed of single-crystal semiconductor mold wafers is carried out, wherein the mold holes for individual emitters are fabricated by utilizing the crystal orientation dependence of the etching rate.

    Abstract translation: 通过模制技术制造场致发射器阵列的方法包括均匀地控制模具孔的形状以获得直径小于100nm的场发射器尖端和钝化的侧边缘。 进行由单晶半导体模具晶片形成的模具基板的重复氧化和蚀刻，其中通过利用蚀刻速率的晶体取向依赖性来制造各个发光体的模具孔。

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