公开(公告)号：US20130265732A1

公开(公告)日：2013-10-10

申请号：US13439557

申请日：2012-04-04

Applicant: Juan A. Herbsommer ,  Robert F. Payne ,  Marco Corsi ,  Baher S. Haroun ,  Hassan Ali

Inventor： Juan A. Herbsommer ,  Robert F. Payne ,  Marco Corsi ,  Baher S. Haroun ,  Hassan Ali

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0239 ,  G02B6/12004 ,  G02B6/1228 ,  H01L2223/6627 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01P3/121 ,  H01P3/16 ,  H05K1/0243 ,  H05K1/025 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/0187 ,  H05K2201/037 ,  H05K2201/09618 ,  H05K2201/10098

Abstract: An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.

Abstract translation: 提供了一种装置。 存在具有封装基板和集成电路（IC）的电路组件。 封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。 电路板也固定到封装衬底。 介质波导固定在电路板上。 电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。

公开(公告)号：US20110018657A1

公开(公告)日：2011-01-27

申请号：US12922588

申请日：2009-03-17

Applicant: Shi Cheng ,  Karl Henrik Kratz ,  Hanna Ali Yousef

Inventor： Shi Cheng ,  Karl Henrik Kratz ,  Hanna Ali Yousef

IPC: H01P3/12 ,  H01P11/00

CPC classification number: H01P3/121 ,  H01P11/002 ,  H05K1/024 ,  H05K3/002 ,  H05K3/0023 ,  H05K3/4076 ,  H05K3/42 ,  H05K2201/037 ,  H05K2201/09618 ,  H05K2203/092 ,  H05K2203/1572 ,  Y10T29/49016

Abstract: A substrate integrated waveguide (10) comprises a top conductive layer (14) and a bottom conductive layer (15) provided on either sides a substrate (11). At least one wall (12, 13) of conductive material is provided in the substrate (11) to define, together with the top and bottom layers (14, 15), the waveguide. The at least one wall (12, 13) comprise a multitude of thin conductive wires densely arranged close to each other in the substrate (11) and having respective short ends connected to the top and bottom layers (14, 15). The high number of wires per surface unit in the wall (12, 13) effectively prevent significant amount of power leakage through the wall (12, 13) during operation of the substrate integrated waveguide (10).

Abstract translation: 衬底集成波导（10）包括设置在衬底（11）的两侧的顶部导电层（14）和底部导电层（15）。 导电材料的至少一个壁（12,13）设置在衬底（11）中以与顶层和底层（14,15）一起限定波导。 所述至少一个壁（12,13）包括在所述基板（11）中彼此靠近彼此密集布置并且具有连接到所述顶层和底层（14,15）的相应短端的多根细导线。 在基板集成波导（10）的操作期间，每个表面单元在壁（12,13）中的大量电线有效地防止了通过壁（12,13）的大量的电力泄漏。

公开(公告)号：US20100032196A1

公开(公告)日：2010-02-11

申请号：US12537391

申请日：2009-08-07

Applicant: Kentaro KANEKO ,  Kazuhiro Kobayashi ,  Yoshiki Okushima ,  Kotaro Kodani

Inventor： Kentaro KANEKO ,  Kazuhiro Kobayashi ,  Yoshiki Okushima ,  Kotaro Kodani

IPC: H05K1/16 ,  H05K1/11 ,  B32B37/00

CPC classification number: H05K1/113 ,  B32B37/02 ,  B32B2457/08 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/02 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/20 ,  H05K3/421 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/037 ,  H05K2201/09527 ,  H05K2201/0979 ,  H05K2201/09981 ,  Y10T156/10 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a multilayer wiring board having a wiring layer, a pad, an insulating layer provided between the wiring layer and the pad, and a plurality of connecting vias provided on the insulating layer and connecting the wiring layer to the pad, the connecting vias are provided on a peripheral edge of the pad.

Abstract translation: 在具有布线层，焊盘，设置在布线层和焊盘之间的绝缘层以及设置在绝缘层上并将布线层连接到焊盘的多个连接通孔的多层布线板中，提供连接通孔 在垫的外围边缘。

公开(公告)号：US20020097117A1

公开(公告)日：2002-07-25

申请号：US10068355

申请日：2002-02-06

Inventor： Luna H. Chiu ,  Yongfei Zhu ,  Xubai Zhang ,  Steven C. Stowell ,  Andrey Kozyrev ,  Somnath Sengupta ,  Louise C. Sengupta

IPC: H01P003/08

CPC classification number: H05K1/162 ,  H01P1/181 ,  H01P3/003 ,  H01P3/06 ,  H01P3/081 ,  H01P3/088 ,  H01P3/122 ,  H01P7/06 ,  H01Q3/44 ,  H05K1/024 ,  H05K2201/0187 ,  H05K2201/037 ,  H05K2203/105 ,  H05K2203/171

Abstract: A tunable dielectric structure includes a first layer of dielectric material, a second layer of dielectric material positioned adjacent to the first layer of dielectric material, with the second layer of dielectric material having a dielectric constant that is less than the dielectric constant of the first layer of dielectric material, and electrodes for applying a controllable voltage across the first dielectric material, thereby controlling a dielectric constant of the first dielectric material, wherein at least one of the electrodes is positioned between the first and second layers of dielectric material. The dielectric materials can be formed in various shapes and assembled in various orientations with respect to each other. The tunable dielectric structure is used in various devices including coaxial cables, cavity antennas, microstrip lines, coplanar lines, and waveguides.

公开(公告)号：US3588757A

公开(公告)日：1971-06-28

申请号：US3588757D

申请日：1968-10-10

Applicant: SIEMENS AG

Inventor： ANDRASCEK ERNST ,  ROSSHAUPTER ERICH

IPC: H01P3/08 ,  H01P3/13 ,  H05K1/02 ,  H05K1/05 ,  H05K1/14 ,  H05K3/42 ,  H05K3/44 ,  H03H7/10 ,  H01P3/00

CPC classification number: H01P3/081 ,  H01P3/13 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/144 ,  H05K3/42 ,  H05K3/427 ,  H05K3/44 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/037 ,  H05K2201/09554 ,  H05K2201/1006

Abstract: A MICROWAVE CIRCUIT EMPLOYING MULTIPLATE TECHNIQUE IN WHICH TWO PLATES OF DIELECTRIC MATERIAL EACH CARRY ON ONE SIDE THEREOF A CONTINUOUS METAL LAYER AND ON THE OTHER SIDE CONDUCTOR TRACKS FORMING MICROWAVE CIRCUIT ELEMENTS, WITH SUCH PLATES BEING SUPERIMPOSED WITH THEIR SIDES CARRYING SUCH CONDUCTOR TRACKS IN OPPOSED RELATION, AND COMPRESSION FORCES APPLIED THERETO, CHARACTERIZED BY THE DIELECTRIC BEING IN THE FORM OF A RELATIVELY THINC COATING ON ONE SIDE OF RESPECTIVE RELATIVELY THICK METAL PLATES AND THE CONDUCTOR TRACKS BEING DISPOSED THE OUTER FACE OF THE RESPECTIVE DIELECTRIC COATINGS, THE RESPECTIVE PLATES AND ASSOCIATED DIELECTRIC COATINGS HAVING PERFORATIONS EXTENDING THERETHROUGH, THE WALLS OF THE APERTURES BEING COATED WITH A METALLIT LAYER EXTENDING FROM SELECTED CONDUCTOR TRACKS TO THE ASSOCIATED METAL PLATE TO CONDUCTIVELY CONNECT THE SAME.

公开(公告)号：EP3341654A1

公开(公告)日：2018-07-04

申请号：EP16838113.5

申请日：2016-08-26

Applicant: Thin Thermal Exchange Pte Ltd ,  Contarino, Aldo

Inventor： CONTARINO, Aldo ,  FREIBERG, Michael

IPC: F21V29/00 ,  F21V29/70 ,  F21V29/74 ,  F21V7/00 ,  F21V13/00

CPC classification number: F21V29/70 ,  F21V29/74 ,  F21V29/85 ,  F21V29/89 ,  F21Y2103/10 ,  F21Y2115/10 ,  H05K1/0204 ,  H05K1/05 ,  H05K1/181 ,  H05K3/06 ,  H05K3/285 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/037 ,  H05K2201/09036 ,  H05K2201/10106 ,  H05K2201/10416 ,  H05K2201/10522 ,  H05K2203/0323 ,  H05K2203/082

Abstract: An evacuated core circuit board (10) for dissipating heat from a heat generating electronic component, the evacuated core circuit board comprising: at least one circuit layer (12) to which the heat generating electronic component (14) is electronically coupled; a base layer (16) a comprising a body structure (19) having a substantially hollow interior (20); and a dielectric layer (18) provided between at least a portion of the circuit layer (12) and the base layer (16), wherein the hollow interior (20) is at least partially evacuated.

公开(公告)号：EP2562470B1

公开(公告)日：2018-04-11

申请号：EP12180113.8

申请日：2012-08-10

Applicant: OSRAM GmbH ,  OSRAM S.P.A. - SOCIETA' RIUNITE OSRAM EDISON CLERICI

Inventor： Katzler, Gerald ,  Scordino, Alessandro ,  Zanon, Franco

IPC: F21S4/00 ,  F21V23/06 ,  H05K3/28 ,  H05K3/40 ,  H01R12/51

CPC classification number: F21S4/20 ,  F21V23/06 ,  F21Y2115/10 ,  H01R12/52 ,  H01R12/718 ,  H01R13/10 ,  H01R13/11 ,  H05K1/0293 ,  H05K1/189 ,  H05K3/284 ,  H05K3/403 ,  H05K2201/037 ,  H05K2201/10106 ,  H05K2201/1031 ,  H05K2203/0228 ,  H05K2203/1316 ,  Y02P70/611 ,  Y10T29/49002

Abstract: A method for producing lighting devices, comprising at least one lighting module (20). The method comprises the stages of: - providing a plurality of lighting modules (20), wherein each lighting module comprises a first set of contacts placed at a first end of said lighting module (20) and a second set of contacts (204c, 204d) placed in corresponding positions at a second end of said lighting module (20); - connecting together a plurality of the lighting modules (20) for forming a series of lighting modules (20), wherein each lighting module (20a) is connected to the next lighting module (20b) by means of interconnecting elements (10) which connect the first set of contacts of each lighting module (20a) to the second set of contacts of the next lighting module (20b); and - cutting the series of lighting modules (20) in lighting devices comprising at least one lighting module (20), wherein the interconnecting elements (10) of the last lighting module of each lighting device are cut along their transverse axes. In particular, the interconnecting elements (10) comprise a base plate and a hollow portion in order to form female connectors when the interconnecting elements (10) are cut along their transverse axes.

公开(公告)号：EP1433221B1

公开(公告)日：2011-11-02

申请号：EP02752720.9

申请日：2002-08-07

Applicant: Intel Corporation

Inventor： BRIST, Gary ,  MEJIA, Charles ,  ALGER, William ,  LONG, Gary

IPC: H01P11/00

CPC classification number: H05K1/0237 ,  H01P11/002 ,  H05K3/0017 ,  H05K2201/037 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09981

Abstract: A method is provided for forming a waveguide in a printed circuit board, This may include forming a trench in a printed circuit substrate and forming at least one metalized surface along the trench. A metalized capping surface may be provided over the trench so as to form the waveguide structure.

公开(公告)号：EP1937040B1

公开(公告)日：2011-02-23

申请号：EP07123279.7

申请日：2007-12-14

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Kornbichler, Andreas ,  Nalezinski, Martin ,  Richter, Olaf ,  Ziroff, Andreas Dr.

IPC: H05K1/02

CPC classification number: H05K1/0243 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3442 ,  H05K3/4697 ,  H05K2201/037 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/10371

公开(公告)号：EP2258022A1

公开(公告)日：2010-12-08

申请号：EP09722528.8

申请日：2009-03-17

Applicant: Cheng, Shi ,  Kratz, Karl Henrik ,  Yousef, Hanna Ali

Inventor： Cheng, Shi ,  Kratz, Karl Henrik ,  Yousef, Hanna Ali

IPC: H01P11/00 ,  B81C1/00 ,  H01P3/12 ,  H05K1/02 ,  H05K3/40

CPC classification number: H01P3/121 ,  H01P11/002 ,  H05K1/024 ,  H05K3/002 ,  H05K3/0023 ,  H05K3/4076 ,  H05K3/42 ,  H05K2201/037 ,  H05K2201/09618 ,  H05K2203/092 ,  H05K2203/1572 ,  Y10T29/49016

Abstract: A substrate integrated waveguide (10) comprises a top conductive layer (14) and a bottom conductive layer (15) provided on either sides a substrate (11). At least one wall (12, 13) of conductive material is provided in the substrate (11) to define, together with the top and bottom layers (14, 15), the waveguide. The at least one wall (12, 13) comprise a multitude of thin conductive wires densely arranged close to each other in the substrate (11) and having respective short ends connected to the top and bottom layers (14, 15). The high number of wires per surface unit in the wall (12, 13) effectively prevent significant amount of power leakage through the wall (12, 13) during operation of the substrate integrated waveguide (10).