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公开(公告)号：KR1020110046873A
公开(公告)日：2011-05-06
申请号：KR1020090103567
申请日：2009-10-29
Applicant: 고려대학교 산학협력단
CPC classification number: H01L27/222 , H01L43/12
Abstract: PURPOSE: An electronic device, memory device, and manufacturing method thereof are provided to prevent the formation of a physical non-planar structure of an upper material layer due to an uneven part of a lower laminate. CONSTITUTION: A functional layer(2) is formed on a substrate(1). The bottom of both ends of the functional layer contacts two electrodes(3) buried in a groove(1a) of the substrate. A first material layer is formed by filling a first electronic material in the groove. A second material layer of a fixed pattern is formed by a second electronic material on one side of the substrate.
Abstract translation: 目的：提供电子设备，存储器件及其制造方法，以防止由于下层叠体的不均匀部分而形成上层材料的物理非平面结构。 构成：在基板（1）上形成功能层（2）。 功能层的两端的底部接触埋在基板的凹槽（1a）中的两个电极（3）。 通过在槽中填充第一电子材料形成第一材料层。 固定图案的第二材料层由衬底的一侧上的第二电子材料形成。
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公开(公告)号：KR100932898B1
公开(公告)日：2009-12-21
申请号：KR1020070077171
申请日：2007-07-31
Applicant: 한국전자통신연구원 , 고려대학교 산학협력단
IPC: B82B3/00 , H01L21/027
Abstract: A formation method of ZnO nanowire network pattern is provided to form ZnO nanowire network pattern and device of a desired shape and size at a low temperature with a stable yield by using a lithographic process and a sol-gel method. A formation method of ZnO nanowire network pattern comprises steps of: forming a photoresist pattern exposing a part of a substrate on the substrate; molding the ZnO nanowire network on a photoresist pattern and an exposed part of the substrate by a sol-gel method; and removing the photoresist pattern and forming the ZnO nanowire network pattern on the substrate. The step for forming the photoresist pattern comprises steps of: coating a photoresist on the substrate; exposing the photoresist; and developing the exposed photoresist.
Abstract translation: 提供一种ZnO纳米线网络图案的形成方法，以通过使用光刻工艺和溶胶 - 凝胶方法在低温下以稳定的产率形成期望形状和尺寸的ZnO纳米线网络图案和器件。 一种ZnO纳米线网络图案的形成方法，包括以下步骤：在基板上形成暴露部分基板的光刻胶图案; 通过溶胶 - 凝胶方法将ZnO纳米线网络模制在光刻胶图案和衬底的暴露部分上; 并去除光致抗蚀剂图案并在衬底上形成ZnO纳米线网状图案。 形成光刻胶图案的步骤包括以下步骤：在衬底上涂覆光刻胶; 暴露光致抗蚀剂; 并显影曝光的光刻胶。
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公开(公告)号：KR1020090121677A
公开(公告)日：2009-11-26
申请号：KR1020080047693
申请日：2008-05-22
Applicant: 고려대학교 산학협력단
IPC: H01L29/786
CPC classification number: H01L51/0048 , H01L29/0669 , H01L29/458 , H01L29/4908 , H01L51/0097 , H01L51/052 , H01L51/055 , H01L51/102 , H01L51/105
Abstract: PURPOSE: A carbon nano tube thin film transistor is provided to increase an aperture ratio of a pixel by allowing all conductive materials and a semiconductor material to include CNT and having a flexible structure while being transparent. CONSTITUTION: A CNT thin film transistor comprises a channel layer, a source / drain electrode, a gate layer, a gate isolation layer, and a transparency flexible substrate. The channel layer by the semiconductor CNT forms an electrical path associated with the transparent organic material and the organic material. The source / drain electrodes(21, 22) is connected with both side of the channel electrically by the conductivity CNT. The source / drain electrode by the conductivity CNT forms an electrical path associated with the organic material and the transparency organic material. A gate layer by the conductivity CNT corresponds to the channel layer, and a gate layer by the conductivity CNT is connected with both sides of the channel electrically.
Abstract translation: 目的：提供一种碳纳米管薄膜晶体管，通过允许所有导电材料和半导体材料包括CNT并且具有柔性结构同时透明化以增加像素的孔径比。 构成：CNT薄膜晶体管包括沟道层，源极/漏极，栅极层，栅极隔离层和透明柔性基板。 由半导体CNT形成的沟道层形成与透明有机材料和有机材料相关联的电路径。 源极/漏极（21,22）通过导电性CNT电连接于沟道的两侧。 源极/漏极通过导电CNT形成与有机材料和透明有机材料相关联的电路径。 通过导电性CNT的栅极层对应于沟道层，并且通过导电性CNT的栅极层与沟道的两侧电连接。
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公开(公告)号：KR1020080052251A
公开(公告)日：2008-06-11
申请号：KR1020070061450
申请日：2007-06-22
Applicant: 한국전자통신연구원 , 고려대학교 산학협력단
IPC: H01L21/027 , B82Y40/00
CPC classification number: H01L21/0274 , B82Y40/00 , G03F7/70283 , G03F7/705
Abstract: A method for manufacturing an electronic device using a nanowire is provided to reduce a manufacturing cost and a manufacturing time for the electronic device by reducing a process using an E-beam. An electrode is formed on a substrate(S11). Plural nanowires are applied on the substrate on which the electrode is formed(S12). An image with respect to the substrate on which the nanowire and the electrode are formed is captured(S13). A virtual connection line connecting the nanowire to the electrode is drawn on the image by using an electrode pattern simulated through a computer program(S14). A photoresist for an E-beam is applied onto the substrate(S15). The photoresist formed on a position corresponding to the virtual connection line and the electrode pattern is removed by an E-beam lithography process(S16). A metal layer is deposited on the substrate(S17). The photoresist remaining on the substrate is removed by a lift-off process(S18).
Abstract translation: 提供一种使用纳米线制造电子装置的方法，通过减少使用电子束的处理来降低电子装置的制造成本和制造时间。 在基板上形成电极（S11）。 在形成电极的基板上施加多个纳米线（S12）。 拍摄相对于其上形成有纳米线和电极的基板的图像（S13）。 通过使用通过计算机程序模拟的电极图案，在图像上画出将纳米线连接到电极的虚拟连接线（S14）。 将用于电子束的光致抗蚀剂施加到基板上（S15）。 通过电子束光刻处理去除在与虚拟连接线和电极图案对应的位置上形成的光致抗蚀剂（S16）。 在基板上沉积金属层（S17）。 通过剥离工艺去除残留在基板上的光致抗蚀剂（S18）。
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公开(公告)号：KR1020080052250A
公开(公告)日：2008-06-11
申请号：KR1020070061440
申请日：2007-06-22
Applicant: 한국전자통신연구원 , 고려대학교 산학협력단
CPC classification number: H01L29/0669 , B82Y10/00 , H01L21/02603
Abstract: A method for fabricating a nano wire array device is provided to embody a large-scale nano wire array device even when a nano wire is not parallel with an electrode line by selectively etching a nano wore on a substrate and by patterning an electrode line in a manner that the electrode becomes vertical to the electrode line to improve a probability that the electrode is connected to the nano wire. A nano wire solution including a nano wire(50) is deposited on a substrate. A first etch region of a stripe type is formed on the substrate to pattern the nano wire. A drain electrode line(100) and a source electrode line(200) are formed at both sides of the patterned nano wire, parallel with each other. One end of a plurality of drain electrodes(110) is connected to the drain electrode line wherein the drain electrode comes in contact with at least one nano wire. One end of a plurality of source electrodes(210) is connected to the source electrode line wherein the source electrode comes in contact with the nano wire in contact with the drain electrode. A second etch region is formed between the pair of drain electrodes and source electrodes so that the pair of drain electrodes and source electrodes don't contact each other electrically. An insulation layer(800) is formed on the substrate. A gate electrode(300) is formed on the insulation layer, disposed between the source and drain electrodes in contact with the nano wire.
Abstract translation: 提供一种制造纳米线阵列器件的方法，即使当纳米线不与电极线并联时，通过选择性地蚀刻衬底上的纳米穿孔并且通过将电极线图案化，以体现大规模纳米线阵列器件 电极变得垂直于电极线的方式，以提高电极连接到纳米线的可能性。 包括纳米线（50）的纳米线溶液沉积在基底上。 在衬底上形成条纹型的第一蚀刻区域以对纳米线进行图案化。 在图案化的纳米线的两侧，彼此平行地形成漏电极线（100）和源电极线（200）。 多个漏电极（110）的一端连接到漏极电极线，其中漏电极与至少一个纳米线接触。 多个源极（210）的一端与源电极线连接，源极与漏极接触的纳米线接触。 在一对漏电极和源电极之间形成第二蚀刻区域，使得该对漏电极和源极电极不彼此接触。 在基板上形成绝缘层（800）。 栅电极（300）形成在绝缘层上，设置在与纳米线接触的源极和漏极之间。
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Patent Agency Ranking
公开(公告)号：KR1020140069781A
公开(公告)日：2014-06-10
申请号：KR1020120137484
申请日：2012-11-30
Applicant: 고려대학교 산학협력단
IPC: H01M4/134 , H01M4/1395 , H01M4/64 , H01M10/052
CPC classification number: H01M4/134 , H01M4/1395 , H01M4/386 , H01M4/661 , H01M10/0525 , Y02E60/122
Abstract: An anode structure for a lithium secondary battery comprises a base, a metal current collector projected from the base and having mutually separated multiple projections, and an anode active material layer formed to be conformal along the upper surface of the base and the projections. Accordingly, the lifetime of the lithium secondary battery including the anode structure for a lithium secondary battery can be improved.
Abstract translation: 锂二次电池的阳极结构包括：底座，从基座突出并具有相互分离的多个突起的金属集流体;以及阳极活性物质层，其形成为沿着基底的上表面和突出部共形。 因此，可以提高包括锂二次电池的阳极结构的锂二次电池的寿命。
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公开(公告)号：KR101213139B1
公开(公告)日：2012-12-18
申请号：KR1020100130511
申请日：2010-12-20
Applicant: 고려대학교 산학협력단
IPC: H01L21/28 , H01L29/786
Abstract: 플렉서블기판상의미세전극간격형성방법은, 플렉서블기판상의미리설정된복수의영역에전극층을형성하는단계, 및그림자효과(shdow effect)를이용하여형성된전극층들사이의미리설정된영역에전극층들중 일부와연결된연장전극층을증착하여형성하는단계를포함한다. 그림자효과를이용하여이미형성된전극의일측에연장된전극을추가로형성함으로써, 공정단계가간단하고공정비용이적게들어대량생산이가능하면서도, 아세톤등을이용한화학공정이필요없어플렉서블기판에도적용가능하게된다.
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公开(公告)号：KR1020120068176A
公开(公告)日：2012-06-27
申请号：KR1020100129671
申请日：2010-12-17
Applicant: 고려대학교 산학협력단
CPC classification number: G01C9/02 , B82B3/00 , G01R19/0084 , H01L29/0669
Abstract: PURPOSE: A tilt sensor and a manufacturing method thereof are provided to reduce toxic material generation and manufacturing costs because an additional semiconductor process is not existed. CONSTITUTION: A tilt sensor comprises substrates(110) facing each other, nano wires(120), a current applying terminal(130), and a voltage measuring terminal(140). The nano wires are respectively formed in each substrate, thereby contacting to each other and comprising a piezoelectric characteristic. The current applying terminal applies a current between the substrates. The voltage measuring terminal is arranged in a different position on the substrate and measures a voltage between the substrates.
Abstract translation: 目的：提供倾斜传感器及其制造方法，以减少有毒物质产生和制造成本，因为不存在附加的半导体工艺。 构成：倾斜传感器包括彼此面对的基板（110），纳米线（120），电流施加端子（130）和电压测量端子（140）。 纳米线分别形成在每个基板中，从而彼此接触并包括压电特性。 电流施加端子在基板之间施加电流。 电压测量端子布置在基板上的不同位置，并测量基板之间的电压。
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公开(公告)号：KR101147314B1
公开(公告)日：2012-05-18
申请号：KR1020100104029
申请日：2010-10-25
Applicant: 고려대학교 산학협력단
IPC: H01L21/3205 , H01L21/28
CPC classification number: H01L23/4824 , B81C1/00166 , H01L24/06 , H01L2924/00013 , H01L2924/01322 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
Abstract: Provided is a vertical electrode structure using a trench and a method of manufacturing the vertical electrode structure. The method of forming a vertical electrode structure using a trench includes steps of: forming the trench on a predetermined region of a semiconductor substrate; and forming electrode layers in predetermined regions of inner and outer portions of the trench. In this manner, the electrode deposition in the vertical direction is established by using the trench, so that it is possible to form a deposited electrode having a size of several hundred nm or less by a short processing time and a low processing cost.
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公开(公告)号：KR101105220B1
公开(公告)日：2012-01-13
申请号：KR1020100022291
申请日：2010-03-12
Applicant: 고려대학교 산학협력단
IPC: H01L31/00
CPC classification number: G01N27/127 , B82Y30/00 , G01N27/4146
Abstract: 본 발명은 나노 물질을 브리지 회로의 저항으로 적용한 센서 시스템을 공개한다. 본 발명은 환경 변화에 대한 반응성이 뛰어난 나노 물질을 반응 물질로 이용함으로써, 보다 미세한 환경 변화에 대해서도 신뢰할 수 있는 측정 결과를 얻을 수 있다. 또한, 본 발명은 나노 물질을 센서에 많이 이용되는 브리지회로의 저항으로 이용하고, 대상 물질의 측정에 이용되는 나노 물질 영역을 제외한 나머지 영역은 유전체로 매립하여 외부 환경에 노출되지 않도록 보호함으로써, 시간이 지남에 따라서 발생하는 센서의 성능 열화를 최소화하였다. 또한, 본 발명은 나노 물질 위에 형성된 게이트에 전압을 인가하여 나노 물질에 전계를 형성함으로써, 나노 물질의 저항을 변화시킬 수 있다. 따라서, 휘트스톤 브리지 회로의 저항을 구성하는 나노 물질의 저항을 사용자의 의도대로 설정할 수 있으며, 이에 따라서 성능 열화에 대한 저항값을 보정함으로써, 성능 열화 및 외부 잡음에 의한 측정값의 변화를 배제하고, 실제로 외부 환경 변화에 의해서 변화된 저항값만을 측정하고, 저항값에 대응되는 대상 물질의 존재 여부 및 농도를 측정할 수 있으므로, 보다 신뢰성 있는 측정이 가능하다. 또한, 본 발명은 휘트스톤 브리지 회로의 내부 평형 조건을 자동으로 조절할 수 있는 회로 장치와 하나의 반도체칩에 일체로 구현되어, 사용자가 일일이 조건을 설정할 필요없이 자동으로 오차를 보정할 수 있다.
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