-
公开(公告)号：KR1020050041797A
公开(公告)日：2005-05-04
申请号：KR1020030077072
申请日：2003-10-31
Applicant: 삼성전자주식회사
IPC: G11B20/10
CPC classification number: G11B27/105 , G11B20/1217 , G11B27/329
Abstract: 확장 검색 기능을 제공하는 메타 정보 및 서브 타이틀 정보가 기록된 저장 매체 및 그 재생 장치가 개시된다.
본 발명에 따른 동영상 정보가 기록된 저장 매체는, 동영상 정보; 상기 동영상 정보에 대한 확장 검색 기능을 제공하기 위한 메타 정보; 및 상기 동영상 정보에 대한 자막을 제공하기 위한 서브 타이틀 정보를 포함하며, 상기 메타 정보 및 상기 서브 타이틀 정보는 별도의 파일로 분리되어 기록되는 것을 특징으로 한다.
이에 따라, 다양한 검색 키워드에 의한 확장 검색이 가능하고, 서브 타이틀 정보가 자막 또는 검색 키워드로 사용될 수 있며, 메타 정보의 크기가 줄어 데이터 처리가 용이하다.-
公开(公告)号：KR1020050041359A
公开(公告)日：2005-05-04
申请号：KR1020030076490
申请日：2003-10-30
Applicant: 삼성전자주식회사
IPC: G11B20/10
CPC classification number: G11B27/105 , G11B27/322 , G11B27/329 , G11B27/34 , G11B2220/2562
Abstract: 재생 모드 정보가 설정된 동영상 재생 장치, 저장 매체 및 그 재생 방법이 개시된다.
본 발명에 따른, 재생 모드 정보가 설정된 동영상 재생 장치는, 재생 가능한 데이터의 타입을 나타내는 재생 모드 정보가 기록된 저장 영역; 및 동영상 정보를 재생하기 위한 제1 타입의 데이터 및 상기 동영상 정보를 이용한 부가 기능을 제공하기 위한 제2 타입의 데이터 중 적어도 하나의 타입의 데이터가 기록된 저장 매체로부터, 상기 재생 모드 정보에 기초하여 제1 타입 또는/ 및 제2 타입의 데이터를 선택적으로 재생하는 재생부를 포함하는 것을 특징으로 한다.
이에 따라, 동영상 정보의 재생 또는/ 및 부가 기능을 제공하는 저장 매체를 재생 장치의 종류에 관계없이 원활하게 재생할 수 있다.-
公开(公告)号：KR1020050015889A
公开(公告)日：2005-02-21
申请号：KR1020030056434
申请日：2003-08-14
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: PURPOSE: A method of fabricating a non-volatile memory device having improved threshold voltage uniformity is provided to round an edge of an isolation layer and prevent a thinning effect in the edge of the isolation layer by utilizing a radical oxidation method using oxygen and hydrogen. CONSTITUTION: A high-voltage oxide layer is formed by oxidizing a recessed high-voltage region of a silicon substrate(10). Trenches are formed at a cell and low-voltage region and the recessed high-voltage region, respectively. An isolation layer is formed by filling up the trenches with a gap-fill oxide layer. A tunnel oxide layer(70) is formed on the silicon substrate including the isolation layer by a radical oxidation method. A floating gate, a dielectric layer, and a control gate are formed on the tunnel oxide layer.
Abstract translation: 目的：提供一种制造具有改善的阈值电压均匀性的非易失性存储器件的方法，以便绕隔离层的边缘，并通过利用氧和氢的自由基氧化法来防止隔离层边缘的变薄效应。 构成：通过氧化硅衬底（10）的凹陷高压区域形成高电压氧化层。 沟槽形成在电池和低电压区域以及凹陷的高压区域。 通过用间隙填充氧化物层填充沟槽形成隔离层。 通过自由基氧化法在包含隔离层的硅衬底上形成隧道氧化物层（70）。 在隧道氧化物层上形成浮栅，电介质层和控制栅极。
-
公开(公告)号：KR1020030003920A
公开(公告)日：2003-01-14
申请号：KR1020010039781
申请日：2001-07-04
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: PURPOSE: A shallow trench isolation method is provided to prevent adjacent gates from being short-circuited by silicon residue by completely eliminating an exposed portion of a silicon layer pattern or silicon structure in a dry etch process for forming a gate. CONSTITUTION: A pattern structure in which an oxide layer pattern, a polysilicon layer pattern and the first nitride layer pattern are sequentially stacked is formed on a silicon substrate(30). An oxide barrier layer(40) composed of a nitride layer is consecutively formed on the sidewall and upper surface of the pattern structure and the exposed silicon substrate. The oxide barrier layer exposed to the silicon substrate is etched by using the pattern structure as an etch mask. The silicon substrate is etched to form a trench(42). The inner surface of the trench is oxidized to form a thermal oxide layer on the inner surface of the trench. A field oxide layer filling the trench is formed.
Abstract translation: 目的：提供浅沟槽隔离方法以通过在用于形成栅极的干蚀刻工艺中完全消除硅层图案或硅结构的暴露部分来防止相邻栅极被硅残渣短路。 构成：在硅衬底（30）上形成氧化物层图案，多晶硅层图案和第一氮化物层图案顺序层叠的图案结构。 在图案结构的侧壁和上表面以及暴露的硅衬底上连续地形成由氮化物层构成的氧化物阻挡层（40）。 通过使用图案结构作为蚀刻掩模蚀刻暴露于硅衬底的氧化物阻挡层。 蚀刻硅衬底以形成沟槽（42）。 沟槽的内表面被氧化以在沟槽的内表面上形成热氧化层。 形成填充沟槽的场氧化层。
-
65.发明公开
公开(公告)号：KR1020030002352A
公开(公告)日：2003-01-09
申请号：KR1020010037911
申请日：2001-06-29
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: PURPOSE: A method for isolating a self-aligned shallow trench and a method for fabricating a non-volatile memory device by using the same are provided to form simultaneously a gate and an active region by using a self-aligned shallow trench isolation method. CONSTITUTION: An oxide layer is formed on a semiconductor substrate(100). The first conductive layer is formed on the oxide layer. A stopping layer is formed on the first conductive layer. A hard mask layer and an anti-reflective layer are formed on the stopping layer. A mask pattern is formed by etching the anti-reflective layer and the hard mask layer. A gate oxide layer(102), the first floating gate pattern(104), and a stopping layer pattern are formed by patterning the stopping layer, the first conductive layer, and the oxide layer. A trench(110) is formed by etching the substrate(100) neighboring to the first floating gate pattern(104). A sidewall of the first floating gate pattern(104) is rounded. A trench oxide layer is formed on an inner face of the trench(110). A field oxide layer is formed in the inside of the trench(110). The second floating gate pattern(118) is formed by removing a conductive layer of the field oxide layer. An ONO dielectric layer(120) is formed on the whole surface of the above structure. A control gate layer(122) is formed on the dielectric layer(120). A stack type gate structure is formed by etching the control gate layer(122), the dielectric layer(120), and the second floating gate pattern(118) and the first floating gate pattern.
Abstract translation: 目的：提供一种用于隔离自对准浅沟槽的方法和通过使用该方法制造非易失性存储器件的方法，以通过使用自对准浅沟槽隔离方法同时形成栅极和有源区域。 构成：在半导体衬底（100）上形成氧化物层。 第一导电层形成在氧化物层上。 在第一导电层上形成停止层。 在停止层上形成硬掩模层和抗反射层。 通过蚀刻抗反射层和硬掩模层形成掩模图案。 通过图案化阻挡层，第一导电层和氧化物层，形成栅氧化层（102），第一浮栅图案（104）和阻挡层图案。 通过蚀刻与第一浮栅图案（104）相邻的衬底（100）形成沟槽（110）。 第一浮栅图案（104）的侧壁是圆形的。 沟槽氧化物层形成在沟槽（110）的内表面上。 在沟槽（110）的内部形成场氧化物层。 通过去除场氧化物层的导电层来形成第二浮栅图案（118）。 在上述结构的整个表面上形成ONO电介质层（120）。 在电介质层（120）上形成控制栅层（122）。 通过蚀刻控制栅极层（122），电介质层（120）和第二浮栅图案（118）和第一浮栅图案来形成堆叠型栅极结构。
-
Patent Agency Ranking
公开(公告)号：KR1020020078429A
公开(公告)日：2002-10-18
申请号：KR1020010018788
申请日：2001-04-09
Applicant: 삼성전자주식회사
Inventor： 강만석
IPC: H01L27/115 , H01L21/8247 , H01L29/788
Abstract: PURPOSE: A method for fabricating a semiconductor memory device is provided to prevent electrical damage caused by a short-circuit between floating gates, by making the floating gate not left in an anisotropical etch process. CONSTITUTION: The first insulation layer is formed on a semiconductor substrate. After the first conductive layer having a density gradient is formed on the first insulation layer, the second insulation layer is formed on the first conductive layer. The first insulation layer, the second insulation layer, the first conductive layer and the substrate are selectively etched to form a trench in a predetermined region of the substrate. After an insulation layer sidewall is formed inside the trench, the third insulation layer is formed in the trench. The second insulation layer is eliminated. The second conductive layer is formed on the first conductive layer, extending to the third insulation layer.
Abstract translation: 目的：提供一种用于制造半导体存储器件的方法，以通过使浮动栅极不留在各向异性热蚀刻工艺中来防止由浮动栅极之间的短路引起的电气损坏。 构成：第一绝缘层形成在半导体衬底上。 在第一绝缘层上形成具有密度梯度的第一导电层之后，在第一导电层上形成第二绝缘层。 选择性地蚀刻第一绝缘层，第二绝缘层，第一导电层和衬底，以在衬底的预定区域中形成沟槽。 在沟槽内形成绝缘层侧壁之后，在沟槽中形成第三绝缘层。 消除了第二绝缘层。 第二导电层形成在第一导电层上，延伸到第三绝缘层。
-
公开(公告)号：KR100335999B1
公开(公告)日：2002-05-08
申请号：KR1020000042695
申请日：2000-07-25
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: 자기정렬된 셸로우 트렌치 소자분리 방법 및 이를 이용한 불휘발성 메모리 장치의 제조방법이 개시되어 있다. 반도체 기판 상에 산화막, 제1 실리콘층 및 질화막을 차례로 형성한다. 하나의 마스크를 사용하여 질화막, 제1 실리콘층 및 산화막을 식각하여 산화막 패턴, 제1 실리콘층 패턴 및 질화막 패턴을 형성한다. 상기 마스크를 이용하여 제1 실리콘층 패턴에 인접한 기판의 상부를 식각하여 트렌치를 형성한다. 제1 실리콘층 패턴 및 기판을 선택적으로 식각하여 산화막 패턴을 돌출시킨 후, 트렌치의 내면을 산화시켜 트렌치 열산화막을 형성한다. 트렌치를 매립하는 필드 산화막을 형성한다. 제1 실리콘층 패턴의 측벽이 포지티브 기울기를 갖는 것을 개선하여 후속하는 게이트 식각시 실리콘층의 잔류물에 의해 소자의 전기적 불량이 발생하는 것을 방지할 수 있다.
-
公开(公告)号：KR1020020009214A
公开(公告)日：2002-02-01
申请号：KR1020000042753
申请日：2000-07-25
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: PURPOSE: A gate stack formation method of semiconductor devices is provided to prevent a generation of voids between a polysilicon layer and a metal silicide by using a CVD(Chemical Vapor Deposition) oxide and a thermal oxide. CONSTITUTION: After forming a gate oxide(410) on a semiconductor substrate(400), a polysilicon layer(420) and a metal silicide film(430) are sequentially formed on the gate oxide(410). A silicon nitride(440) and a silicon oxide(450) are sequentially formed on the metal silicide film. By sequentially etching the silicon oxide, the silicon nitride, the metal silicide film and the polysilicon layer, a gate stack is formed. A CVD oxide(470) is formed on the entire surface of the resultant structure. By performing a thermal oxidation, a thermal oxide(480) is formed at both sidewalls of the polysilicon layer(420) and the metal silicide film(430).
Abstract translation: 目的：提供半导体器件的栅堆叠形成方法，以通过使用CVD（化学气相沉积）氧化物和热氧化物来防止在多晶硅层和金属硅化物之间产生空隙。 构成：在半导体衬底（400）上形成栅极氧化物（410）之后，在栅极氧化物（410）上依次形成多晶硅层（420）和金属硅化物膜（430）。 在金属硅化物膜上依次形成氮化硅（440）和氧化硅（450）。 通过依次蚀刻氧化硅，氮化硅，金属硅化物膜和多晶硅层，形成栅叠层。 在所得结构的整个表面上形成CVD氧化物（470）。 通过进行热氧化，在多晶硅层（420）和金属硅化物膜（430）的两个侧壁处形成热氧化物（480）。
-
公开(公告)号：KR1020000061772A
公开(公告)日：2000-10-25
申请号：KR1019990011067
申请日：1999-03-30
Applicant: 삼성전자주식회사
Inventor： 강만석
IPC: H01L21/334
Abstract: PURPOSE: A fabrication method of a semiconductor device is to minimize a threshold voltage variation of MOSFET by maintaining high an impurity concentration of a gate electrode. CONSTITUTION: A trench isolation(102) is formed in an N-type well(100) formed in a P-type semiconductor substrate. A gate oxide layer(104) having a thickness of 50 angstroms is grown in the N-type well with the trench isolation formed therein. A first polycrystalline silicon layer is formed on the upper portion of the resultant material with the gate oxide layer formed thereon. Indium ions are implanted into the N-type well with the first polycrystalline silicon layer formed thereon. The first polycrystalline silicon layer is thinly formed at a thickness of 1000 angstroms so that the Indium ions are penetrated thereinto. A second polycrystalline silicon layer is formed at a thickness of 2000 angstroms to compensate the first polycrystalline silicon layer. A gate electrodes(106a,110a) are formed by patterning the second and the first polycrystalline silicon layers. A self-aligned source and drain region(112) is formed by implanting a B or a BF2 having a low concentration by using the gate electrodes as an ion implantation mask. Then, a sidewall spacer(114) is respectively formed on side walls of the gate electrodes.
Abstract translation: 目的：半导体器件的制造方法是通过保持栅电极的杂质浓度较高来最小化MOSFET的阈值电压变化。 构成：在形成在P型半导体衬底中的N型阱（100）中形成沟槽隔离（102）。 在N型阱中生长厚度为50埃的栅极氧化物层（104），其中形成沟槽隔离。 在其上形成有栅氧化层的所得材料的上部形成第一多晶硅层。 铟离子注入到其中形成有第一多晶硅层的N型阱中。 第一多晶硅层以1000埃的厚度被薄地形成，从而使铟离子进入其中。 以2000埃的厚度形成第二多晶硅层以补偿第一多晶硅层。 通过对第二多晶硅层和第一多晶硅层进行构图来形成栅电极（106a，110a）。 通过使用栅电极作为离子注入掩模注入具有低浓度的B或BF 2来形成自对准源极和漏极区（112）。 然后，在栅电极的侧壁上分别形成侧壁间隔物（114）。
-
公开(公告)号：KR1020000050488A
公开(公告)日：2000-08-05
申请号：KR1019990000410
申请日：1999-01-11
Applicant: 삼성전자주식회사
Inventor： 강만석
IPC: H01L21/336
Abstract: PURPOSE: A method for manufacturing a semiconductor device having a structure of a dual gate is provided to protect a semiconductor substrate by preventing a gate oxidation layer from being deteriorated by penetration of a boron. CONSTITUTION: A method for manufacturing a semiconductor device having a structure of a dual gate comprises the steps of: forming a first insulation layer on a semiconductor substrate; forming a second insulation layer on the first insulation layer by a chemical vapor deposition(CVD) method; performing a heat treatment after ion-injecting a nitrogen to the resultant, and having the nitrogen file up in the boundary between the first insulation layer and the semiconductor substrate; eliminating the first and second insulation layers; and forming a gate insulation layer on the resultant.
Abstract translation: 目的：提供一种制造具有双栅结构的半导体器件的方法，以通过防止栅极氧化层由于硼的穿透而劣化来保护半导体衬底。 构成：制造具有双栅极结构的半导体器件的方法包括以下步骤：在半导体衬底上形成第一绝缘层; 通过化学气相沉积（CVD）方法在所述第一绝缘层上形成第二绝缘层; 在对所得物进行氮离子注入之后进行热处理，并且在第一绝缘层和半导体基板之间的边界内具有氮气文件; 消除第一和第二绝缘层; 并在所得物上形成栅极绝缘层。
-
-
-
-
-
-
-
-
-
Search Results
204
records
(took 0.025 seconds)
