公开(公告)号：KR1020040050405A

公开(公告)日：2004-06-16

申请号：KR1020020078229

申请日：2002-12-10

Applicant: 삼성전자주식회사

Inventor： 이덕형 ,  최시영 ,  이병찬 ,  유종렬 ,  정인수

IPC: H01L21/335

Abstract: PURPOSE: A method for forming a pin structure FET(Field Effect Transistor) is provided to be capable of overcoming the limitation of an exposure process for effectively forming a pin pattern on a substrate. CONSTITUTION: The first dummy pattern is formed on a channel forming region of a substrate(1). The second dummy pattern is formed by carrying out an isotropic etching process on the first dummy pattern. At this time, an active region is partially exposed to the outside through one side of the second dummy pattern. A pin(57) is formed on the active region by carrying out a selective crystal growing process. The second dummy pattern is removed from the resultant structure. A gate isolating layer(59) is formed on the pin. A gate conductive pattern is formed on the resultant structure, wherein the gate conductive pattern crosses the pin.

Abstract translation: 目的：提供一种用于形成pin结构FET（场效应晶体管）的方法，以能够克服用于在衬底上有效地形成针脚图案的曝光过程的限制。 构成：第一虚设图案形成在基板（1）的沟道形成区域上。 通过在第一虚拟图案上进行各向同性蚀刻工艺来形成第二虚设图案。 此时，有源区域通过第二虚设图案的一侧部分地暴露于外部。 通过进行选择性晶体生长处理，在有源区上形成引脚（57）。 从所得到的结构中去除第二伪图案。 在引脚上形成栅绝缘层（59）。 在所得结构上形成栅极导电图案，其中栅极导电图案与销交叉。

公开(公告)号：KR1020040047534A

公开(公告)日：2004-06-05

申请号：KR1020030041211

申请日：2003-06-24

Applicant: 삼성전자주식회사

Inventor： 이병찬 ,  최시영 ,  유종렬 ,  손용훈 ,  정인수 ,  이덕형

IPC: H01L27/108

Abstract: PURPOSE: A semiconductor device with a buried insulation layer pattern is provided to minimize a short channel effect and a punch-through phenomenon generated when a depletion layer in a semiconductor substrate near a drain region expands, by selectively removing a silicon germanium layer formed by an epitaxial growth technology and by forming a buried insulation layer pattern under the drain region. CONSTITUTION: An isolation layer pattern(200') is disposed in a trench for defining an active region, formed in a predetermined region of the semiconductor substrate(100). A gate electrode(214) crosses the active region and the isolation layer pattern. Impurity diffusion layers(240s,240d) are formed in the active region at both sides of the gate electrode. The buried insulation layer pattern(200a) is disposed under at least one of the impurity diffusion layers.

Abstract translation: 目的：提供一种具有掩埋绝缘层图案的半导体器件，以便通过选择性地去除由下列方面形成的硅锗层，从而使漏极区域附近的半导体衬底中的耗尽层扩大时产生的短沟道效应和穿通现象最小化 外延生长技术，并通过在漏极区域下形成掩埋绝缘层图案。 构成：隔离层图案（200'）设置在沟槽中，用于限定形成在半导体衬底（100）的预定区域中的有源区。 栅电极（214）与有源区和隔离层图案交叉。 杂质扩散层（240s，240d）形成在栅电极两侧的有源区中。 掩埋绝缘层图案（200a）设置在至少一个杂质扩散层的下方。

公开(公告)号：KR1020040018806A

公开(公告)日：2004-03-04

申请号：KR1020020050804

申请日：2002-08-27

Applicant: 삼성전자주식회사

Inventor： 이병찬 ,  최시영 ,  김철성 ,  유종렬 ,  이덕형

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/6656

Abstract: PURPOSE: A method for forming a semiconductor device having a metal silicide layer is provided to be capable of preventing the deterioration of the metal silicide layer due to a gate thermal oxidation process. CONSTITUTION: An active region is defined by forming an isolation layer(101) on a semiconductor substrate(100). A plurality of gate patterns are formed at the upper portions of the resultant structure. At this time, each gate pattern is formed by sequentially depositing a gate isolating layer, a gate electrode, and a deposition preventing layer. A gate thermal oxide layer(106) is formed at both sidewalls of each gate electrode. A spacer(108) is formed at both sidewalls of each gate pattern. An epitaxial layer having a predetermined height is the formed on the resultant structure. The upper surface of the gate electrode is exposed by etching the deposition preventing layer. Then, a metal silicide layer(125) is formed at the upper portions of the exposed gate electrode and the epitaxial layer.

Abstract translation: 目的：提供一种用于形成具有金属硅化物层的半导体器件的方法，以能够防止由于栅极热氧化处理而引起的金属硅化物层的劣化。 构成：通过在半导体衬底（100）上形成隔离层（101）来限定有源区。 在所得结构的上部形成有多个栅极图案。 此时，通过依次沉积栅绝缘层，栅电极和防沉积层来形成每个栅极图案。 在每个栅极的两个侧壁处形成栅极氧化物层（106）。 在每个栅极图案的两个侧壁处形成间隔物（108）。 在所得结构上形成具有预定高度的外延层。 通过蚀刻防沉积层来暴露栅电极的上表面。 然后，在暴露的栅电极和外延层的上部形成金属硅化物层（125）。

公开(公告)号：KR1020040013300A

公开(公告)日：2004-02-14

申请号：KR1020020046159

申请日：2002-08-05

Applicant: 삼성전자주식회사

Inventor： 이병찬 ,  최시영 ,  김철성 ,  유종렬 ,  이덕형

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/823425 ,  H01L27/10817 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66659

Abstract: PURPOSE: A metal-oxide-semiconductor(MOS) transistor is provided to improve the capacity by minimizing a defect like punch-through caused by extension of a depletion layer in a drain region and by reducing the resistance with a pad electrode in contact with the drain region. CONSTITUTION: The first silicon layer(100) is formed. A silicon germanium layer(101) is partially formed on the first silicon layer. The second silicon layer(102) is formed on the silicon germanium layer. A gate electrode is formed on the second silicon layer by interposing a gate insulation layer. A source region formed of impurities of the first density is formed under the second silicon layer extended from one side surface of the gate electrode. A drain region formed of impurities of the second density is formed under the second silicon surface extended from the other side surface of the gate electrode, confronting the source region. A blocking layer pattern(108) for controlling the generation of the depletion layer comes in contact with the side surface of the silicon germanium layer, corresponding to the bottom of the drain region.

Abstract translation: 目的：提供一种金属氧化物半导体（MOS）晶体管，以通过使由漏极区域中的耗尽层延伸引起的穿孔等缺陷最小化，并通过与焊接电极接触的电极降低电阻来提高容量 漏区。 构成：形成第一硅层（100）。 硅锗层（101）部分地形成在第一硅层上。 第二硅层（102）形成在硅锗层上。 通过设置栅极绝缘层，在第二硅层上形成栅电极。 在从栅电极的一个侧表面延伸的第二硅层的下方形成由第一密度的杂质构成的源区。 由栅极电极的另一个侧表面延伸的第二硅表面形成有与第二密度杂质形成的漏极区域，面对源极区域。 用于控制耗尽层的产生的阻挡层图案（108）与对应于漏极区域的底部的硅锗层的侧表面接触。

公开(公告)号：KR1020040009870A

公开(公告)日：2004-01-31

申请号：KR1020020044229

申请日：2002-07-26

Applicant: 삼성전자주식회사

Inventor： 이병찬 ,  최시영 ,  김철성 ,  유종렬 ,  김성민

IPC: H01L21/762

Abstract: PURPOSE: A method for isolating elements of a semiconductor device is provided to minimize a punch-through phenomenon between adjacent transistors by forming a silicon epitaxial layer using a selective epitaxial growth method. CONSTITUTION: A trench mask layer is formed on a semiconductor substrate(10). A trench mask pattern(20,30) is formed by patterning the trench mask layer. A trench(40) for limiting an active region is formed by etching the exposed semiconductor substrate(10). A trench spacer is formed on a sidewall of the trench(40) in order to expose a bottom side of the trench. A bottom gap region(60) is formed by etching the exposed bottom side of the trench. A bottom gap region(60) is filled by an epitaxial layer(70).

Abstract translation: 目的：提供一种用于隔离半导体器件的元件的方法，以通过使用选择性外延生长法形成硅外延层来最小化相邻晶体管之间的穿通现象。 构成：在半导体衬底（10）上形成沟槽掩模层。 沟槽掩模图案（20,30）通过图案化沟槽掩模层而形成。 通过蚀刻暴露的半导体衬底（10）形成用于限制有源区的沟槽（40）。 在沟槽（40）的侧壁上形成沟槽间隔物，以便露出沟槽的底侧。 通过蚀刻暴露的沟槽底侧形成底部间隙区域（60）。 底部间隙区域（60）由外延层（70）填充。

公开(公告)号：KR1020020013197A

公开(公告)日：2002-02-20

申请号：KR1020000046680

申请日：2000-08-11

Applicant: 삼성전자주식회사

Inventor： 박정우 ,  유종렬 ,  하정민 ,  최시영

IPC: H01L21/20

CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  Y10S438/933

Abstract: PURPOSE: A method for forming a selective epitaxial growth(SEG) of a semiconductor device is provided to maintain growth selectivity of an epitaxial process and to remarkably improve a growth rate, surface roughness and a groove density of an epitaxial layer, by sequentially injecting source gas and etch gas and by additionally injecting reducing gas. CONSTITUTION: An insulation layer pattern exposing a predetermined region of a semiconductor substrate is formed on the semiconductor substrate. The semiconductor substrate having the insulation layer pattern is loaded to the inside of a reaction chamber. Source gas is injected to the reaction chamber for the first time to form a semiconductor layer on the semiconductor substrate. Etch gas is injected to the chamber for the second time to selectively eliminate the semiconductor layer on the insulation layer pattern. Reducing gas is injected to the chamber for the third time to remove the atoms of the etch gas absorbed to the surface of the semiconductor layer remaining on the exposed semiconductor substrate. The processes for sequentially injecting the source gas, the etch gas and the reducing gas are repeated at least twice.

Abstract translation: 目的：提供一种用于形成半导体器件的选择性外延生长（SEG）的方法，以保持外延工艺的生长选择性，并通过依次注入源极，显着提高外延层的生长速率，表面粗糙度和沟槽密度 气体和蚀刻气体，以及另外注入还原气体。 构成：在半导体衬底上形成暴露半导体衬底的预定区域的绝缘层图案。 具有绝缘层图案的半导体衬底被加载到反应室的内部。 将源气体首次注入反应室，以在半导体衬底上形成半导体层。 第二次将蚀刻气体注入到腔室中以选择性地消除绝缘层图案上的半导体层。 减少气体第三次被注入到腔室中以除去吸附在暴露的半导体衬底上的半导体层的表面的蚀刻气体的原子。 将源气体，蚀刻气体和还原气体顺序喷射的方法重复至少两次。

公开(公告)号：KR1020160135010A

公开(公告)日：2016-11-24

申请号：KR1020150067546

申请日：2015-05-14

Applicant: 삼성전자주식회사

Inventor： 탁용석 ,  유종렬 ,  이현정 ,  박미선 ,  구본영 ,  김선정

IPC: H01L29/78 ,  H01L21/205

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

Abstract: 반도체소자는, 기판상에제공되고일 방향으로연장되는핀 구조체, 상기핀 구조체를가로지르는게이트전극, 상기게이트전극양 측의상기핀 구조체상에제공되는소스/드레인영역들, 및상기소스/드레인영역들의각각과상기핀 구조체사이의배리어층을포함한다. 상기핀 구조체는상기기판과다른격자상수를갖는물질을포함한다. 상기핀 구조체, 상기소스/드레인영역들, 및상기배리어층은게르마늄을포함한다. 상기배리어층내 게르마늄농도는상기핀 구조체내 게르마늄농도보다크고, 상기소스/드레인영역들각각내 게르마늄의최대농도보다작다.

Abstract translation: 半导体器件包括在衬底上并沿第一方向延伸的翅片结构，在翅片结构上交叉的栅电极，在栅电极的相对侧的翅片结构上的源/漏区和鳍结构之间的阻挡层 和源极/漏极区域中的每一个。 翅片结构包括具有与衬底的晶格常数不同的晶格常数的材料，鳍结构，源/漏区和阻挡层包括锗，并且阻挡层中的锗浓度大于翅片结构中的锗浓度 并且在每个源极/漏极区域中小于最大锗浓度。

公开(公告)号：KR1020160125208A

公开(公告)日：2016-10-31

申请号：KR1020150056097

申请日：2015-04-21

Applicant: 삼성전자주식회사

Inventor： 박미선 ,  유종렬 ,  이현정 ,  탁용석 ,  구본영 ,  김선정

IPC: H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791

Abstract: 기판상에서로평행하게연장하는핀 액티브영역들, 상기핀 액티브영역들을정의하는아이솔레이션영역, 상기핀 액티브영역들과수직으로교차하고서로평행하게연장하는게이트패턴들, 상기게이트패턴들사이의상기핀 액티브영역들상의소스/드레인영역들및 상기핀 액티브영역들의측면들과접하고, 상기핀 액티브영역들사이의상기아이솔레이션영역의표면을덮는핀 액티브스페이서들을포함하고, 상기핀 액티브스페이서들의최상부레벨들은상기핀 액티브영역들과상기소스/드레인영역들간의경계면들보다높고, 및상기아이솔레이션영역의표면은상기소스/드레인영역들의하면들보다낮은반도체소자가설명된다.

Abstract translation: 半导体器件可以包括在衬底上彼此平行延伸的翅片有源区域，翅片有源区域之间的隔离区域，与翅片有源区域相交并且彼此平行延伸的栅极图案，翅片有源区域之间的源极/漏极区域在 所述栅极图案和鳍状有源区间隔物接触所述翅片有源区域的侧表面并形成在所述鳍片活动区域之间的所述隔离区域的表面上。 翅片有源区间隔物的最上层可以高于翅片有源区和源极/漏极区之间的界面。 隔离区域的上表面可以低于源/漏区域的底表面。

公开(公告)号：KR100854498B1

公开(公告)日：2008-08-26

申请号：KR1020060084786

申请日：2006-09-04

Applicant: 삼성전자주식회사

Inventor： 부경호 ,  이선길 ,  유종렬 ,  이덕형 ,  연국현

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/12 ,  H01L29/1083 ,  H01L29/78

Abstract: 펀치쓰루 억제용 불순물 영역을 갖는 선택 트랜지스터들을 구비하는 낸드형 플래쉬 메모리 소자가 제공된다. 상기 소자는 반도체 기판 내에 형성된 제1 및 제2 불순물 영역들 및 상기 제1 및 제2 불순물 영역들 사이의 상기 반도체 기판 상부에 배치된 제1 및 제2 선택 게이트 패턴들을 구비한다. 상기 제1 및 제2 선택 게이트 패턴들은 각각 상기 제1 및 제2 불순물 영역들에 각각 인접하도록 배치된다. 상기 제1 및 제2 선택 라인들 사이에 복수개의 셀 게이트 패턴들이 배치된다. 상기 반도체 기판 내에 상기 제1 불순물 영역을 둘러싸는 제1 펀치쓰루 억제용 불순물 영역이 제공된다. 상기 제1 펀치쓰루 억제용 불순물 영역은 상기 제1 불순물 영역에 인접한 상기 제1 선택 게이트 패턴의 제1 가장자리와 중첩한다. 상기 반도체 기판 내에 상기 제2 불순물 영역을 둘러싸는 제2 펀치쓰루 억제용 불순물 영역이 제공된다. 상기 제2 펀치쓰루 억제용 불순물 영역은 상기 제2 불순물 영역에 인접한 상기 제2 선택 게이트 패턴의 제1 가장자리와 중첩한다.

公开(公告)号：KR100764059B1

公开(公告)日：2007-10-09

申请号：KR1020060092481

申请日：2006-09-22

Applicant: 삼성전자주식회사

Inventor： 이덕형 ,  이선길 ,  유종렬 ,  이병찬 ,  정인수

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L29/66795 ,  H01L27/10826 ,  H01L27/10879

Abstract: A semiconductor device and its forming method are provided to prevent the generation of GIDL(Gate Induced Drain Leakage), to reduce the influence of electric field on a gate electrode, and to keep a threshold voltage in a high level. A semiconductor pin(107) is formed on a semiconductor substrate(101). A gate electrode(123) crosses the semiconductor pin. The gate electrode has surfaces opposite to both sidewalls of the semiconductor pin. A first epitaxial layer(131) is grown from the semiconductor pin of both sides of the gate electrode. A second epitaxial layer(137) is grown from the first epitaxial layer. An ion implantation is performed on the first and second epitaxial layers. An insulating layer is interposed between the first and second epitaxial layers. The insulating layer has an opening portion capable of exposing partially the first epitaxial layer to the outside.

Abstract translation: 提供半导体器件及其形成方法以防止产生GIDL（栅极引起的漏极泄漏），以减小栅极电场的电场影响，并将阈值电压保持在较高水平。 在半导体衬底（101）上形成半导体管脚（107）。 栅电极（123）与半导体引脚交叉。 栅电极具有与半导体引脚的两个侧壁相对的表面。 从栅电极的两侧的半导体引脚生长第一外延层（131）。 从第一外延层生长第二外延层（137）。 在第一和第二外延层上进行离子注入。 绝缘层插入在第一和第二外延层之间。 绝缘层具有能够将第一外延层部分地暴露于外部的开口部。