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公开(公告)号：KR100532564B1
公开(公告)日：2005-12-01
申请号：KR1020040037571
申请日：2004-05-25
Applicant: 한국전자통신연구원
IPC: H01L21/336
CPC classification number: H01L29/785 , H01L29/66818
Abstract: 본 발명은 다중 게이트 모스 트랜지스터 및 그의 제조 방법에 관한 것으로, 단결정 실리콘 패턴의 형태와 실리콘의 결정 방향에 따른 열산화 속도 차이를 이용하여 유선(∩) 형태의 채널, 점차 증가하는 형태의 확장 영역 및 상승된 구조의 소스 및 드레인을 구현한다. 채널이 유선(∩) 형태로 형성됨으로써 전계의 집중으로 인한 소자의 신뢰성 저하가 방지되며, 채널의 상부와 양 측벽이 게이트 전극으로 둘러싸여지기 때문에 게이트 전압에 의한 전류 구동 능력이 우수해진다. 또한, 크기가 증가된 확장 영역으로 인해 전류 밀집 현상이 방지되며, 상승된 소스 드레인 구조에 의해 소스 및 드레인 직렬 저항이 감소되어 전류 구동 능력이 증대된다.
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公开(公告)号：KR1020050066932A
公开(公告)日：2005-06-30
申请号：KR1020040015070
申请日：2004-03-05
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/78696 , H01L21/0415 , H01L21/28255
Abstract: 본 발명은 균일 두께를 가진 스트레인드 실리콘 채널이 형성가능한 반도체 소자용 기판 제조방법 및 이를 이용한 반도체 소자의 제조방법에 관한 것으로, 본 발명의 반도체 소자용 기판 제조방법은 제 1 실리콘 기판 상에 도핑된 SiGe층 및 스트레인드 실리콘 채널층을 에피텍셜 공정으로 차례로 성장하는 단계와, 수소 또는 질소 이온을 상기 제 1 실리콘 기판의 일영역에 주입하여 이온 주입층이 상기 제 1 실리콘 기판을 2개의 영역으로 양분하도록 하는 단계와, 제 1 산화막이 형성된 제 2 실리콘 기판을 상기 제 1 실리콘 기판의 상기 스트레인드 실리콘 채널층이 형성된 면과 대향하도록 서로 부착하는 단계와, 제 1 실리콘 기판과 제 2 실리콘 기판을 이온 주입층을 기준으로 분리하는 단계를 포함한다.
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公开(公告)号：KR1020050064564A
公开(公告)日：2005-06-29
申请号：KR1020030096035
申请日：2003-12-24
Applicant: 한국전자통신연구원
IPC: G09G3/30
CPC classification number: G09G3/30 , G09G2310/027 , G09G2320/0276
Abstract: 본 발명은 디지털 신호를 아날로그 신호로 변환하고 이 변환과정에서 동시에 램프 신호를 생성하는 디지털-아날로그 변환/램프 회로를 구비하는 능동 구동형 EL의 소스 구동회로를 제공한다. 이를 통해 온도나 문턱전압 변동에 무관하고 종래의 램프 회로를 사용하지 않을 수 있어 고집적도가 가능하도록 할 수 있다.
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公开(公告)号：KR100466540B1
公开(公告)日：2005-01-15
申请号：KR1020020051029
申请日：2002-08-28
Applicant: 한국전자통신연구원
IPC: H03K19/00
CPC classification number: H03K19/0016
Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.
Abstract translation: 输入和输出端口电路 输入和输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于电源开关电路 根据功率模式控制信号选择性地提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值和输入/输出寄存器的值来确定信号的方向;输出控制 电路根据控制寄存器的值和信号方向控制电路的输出进行驱动;以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以仅使用单个输出驱动电路同时驱动，并且单个输出驱动电路构造为多个级并且由输出控制寄存器选择性地驱动。 因此，可以节省功耗。
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公开(公告)号：KR1020040046176A
公开(公告)日：2004-06-05
申请号：KR1020020074015
申请日：2002-11-26
Applicant: 한국전자통신연구원
IPC: H01L21/205
Abstract: PURPOSE: An apparatus for manufacturing a semiconductor device and a manufacturing method of the semiconductor device using the same are provided to be capable of effectively forming an insulating layer at a low temperature. CONSTITUTION: An apparatus for manufacturing a semiconductor device is provided with a reaction furnace(20), a wafer support part(40) installed in the reaction furnace for supporting a wafer, a heating part(50) for heating the wafer, a power supply(55) for supplying power to the heating part, and a gas flow part(10) for flowing reaction gas. The apparatus for manufacturing a semiconductor device further includes a plasma generating part(200) for transforming the reaction gas supplied from the gas flow part into ion reticle and supplying the ion reticle into the reaction furnace, and an ion removing part(300) for controlling the excessive flow of the ion reticle into the reaction furnace.
Abstract translation: 目的：提供一种用于制造半导体器件的装置和使用其的半导体器件的制造方法，以能够在低温下有效地形成绝缘层。 构成：半导体装置的制造装置具备反应炉（20），安装在用于支撑晶片的反应炉内的晶片支撑部（40），加热晶片的加热部（50），电源 （55），用于向加热部供电;以及气流部（10），用于使反应气体流动。 本发明的半导体装置的制造装置还包括：等离子体产生部（200），用于将从气体流供给的反应气体变换为离子掩模版并将离子掩模版供给到反应炉中;以及离子去除部（300） 离子掩模版过度流入反应炉。
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Patent Agency Ranking
公开(公告)号：KR100399583B1
公开(公告)日：2003-09-26
申请号：KR1019990053515
申请日：1999-11-29
Applicant: 한국전자통신연구원
IPC: H01L27/085
CPC classification number: H01L29/7813 , H01L29/0847 , H01L29/42368
Abstract: The present invention relates to a method of fabricating a vertical TI)MOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS according to the present invention is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.
Abstract translation: 本发明涉及一种使用侧壁间隔件和自对准技术以及TDMOS功率器件制造垂直TI功率器件的方法。 根据本发明的TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。 在此过程中，高浓度的离子注入到沟槽的底部使得在栅极的底部和拐角处生长出厚的氧化膜，从而可以改善器件的电特性，特别是漏电流和击穿电压。 而且，可以大大减少工艺步骤以降低工艺成本，可以实现高度集成，并且可以提高装置的可靠性。
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公开(公告)号：KR1020020054110A
公开(公告)日：2002-07-06
申请号：KR1020000082805
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/7813 , H01L29/4232 , H01L29/4238
Abstract: PURPOSE: A trench gate power device using hydrogen annealing and self-aligned technology is provided to remarkably reduce fabricating cost, by using three masks of fabricating a trench gate power metal oxide semiconductor field effect transistor(MOSFET), and to improve on-resistance by forming a source while a sidewall oxide layer and the self-aligned technology are used. CONSTITUTION: A hydrogen annealing process is performed regarding a trench to round the corner portion of the trench so that a uniform oxide layer is grown on the trench to improve an electrical characteristic. The annealing process is performed by using a pull-back region which is generated by removing a trench sidewall oxide layer.
Abstract translation: 目的：通过使用制造沟槽栅极功率金属氧化物半导体场效应晶体管（MOSFET）的三个掩模，提供使用氢退火和自对准技术的沟槽栅极功率器件，以显着降低制造成本，并通过 在使用侧壁氧化物层和自对准技术的同时形成源极。 构成：对沟槽进行氢退火处理以使沟槽的拐角部分圆周化，使得在沟槽上生长均匀的氧化物层以改善电特性。 通过使用通过去除沟槽侧壁氧化物层产生的拉回区域来执行退火处理。
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公开(公告)号：KR1020020049162A
公开(公告)日：2002-06-26
申请号：KR1020000078264
申请日：2000-12-19
Applicant: 한국전자통신연구원
IPC: H01L27/04
Abstract: PURPOSE: A method for fabricating a power integrated circuit is provided to remarkably reduce a high temperature annealing process for fabricating the power integrated circuit, by mixing a non-reduced surface field(RESURF) n-lateral double diffused metal oxide semiconductor(LDMOS) transistor and a RESURF p-LDMOS transistor. CONSTITUTION: The power integrated circuit includes the RESURF LDMOS transistor using a silicon-on-insulator, the non-RESURF LDMOS transistor of an opposite type to the RESURF LDMOS transistor and a logic complementary metal oxide semiconductor(CMOS). The regions where the logic CMOS as a low voltage device and an LDMOS transistor as a high power device are fabricated are doped with the same impurity type in a silicon substrate.
Abstract translation: 目的：提供一种制造功率集成电路的方法，通过混合非还原表面场（RESURF）n侧双扩散金属氧化物半导体（LDMOS）晶体管，显着降低制造功率集成电路的高温退火工艺 和RESURF p-LDMOS晶体管。 构成：功率集成电路包括使用绝缘体上硅的RESURF LDMOS晶体管，与RESURF LDMOS晶体管相反类型的非RESURF LDMOS晶体管和逻辑互补金属氧化物半导体（CMOS）。 制造作为低电压器件的逻辑CMOS和作为高功率器件的LDMOS晶体管的区域在硅衬底中掺杂相同的杂质类型。
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公开(公告)号：KR1020020043996A
公开(公告)日：2002-06-14
申请号：KR1020000073473
申请日：2000-12-05
Applicant: 한국전자통신연구원
IPC: H01L21/336
Abstract: PURPOSE: A method for fabricating a high-current power integrated circuit is provided to decrease the size of a high-current integrated circuit(IC) chip, by integrating a high-current trench gate DMOS power device and high-voltage lateral double diffused MOS(LDMOS) and complementary MOS(CMOS) devices in an n-type epitaxial layer on a p-type silicon substrate. CONSTITUTION: A thick thermal oxide layer is grown on the p-type silicon substrate(1) and a photolithography process is performed regarding the thermal oxide layer to define an n-type buried layer(2). The density of the n-type buried layer is controlled according to a breakdown voltage. Phosphorous ions are implanted into the n-type buried layer and are diffused in an oxidation atmosphere so that a phosphorous-doped n-type epitaxial layer is grown. An n-well and a p-well are formed, wherein a high temperature heat treatment process is performed to make the junction of the n-type buried layer out-diffused to a lower portion of a gate electrode. A trench device is isolated. A p-body junction is formed as a channel region of a trench gate DMOS. A field oxide layer region is defined and a field threshold voltage is controlled. An oxide layer is grown. A gate oxide layer of the high-voltage LDMOS and CMOS devices is grown, and a threshold voltage is controlled to form the gate electrode. An LDD junction is formed and a sidewall oxide layer(17) is formed. The source and drain of the CMOS and LDMOS trench gate DMOS devices are joined and a metal interconnection is formed.
Abstract translation: 目的：提供一种大电流功率集成电路的制造方法，通过集成高电流沟槽栅极DMOS功率器件和高电压侧向双扩散MOS（MOS）功率来减小大电流集成电路（IC）芯片的尺寸 （LDMOS）和互补MOS（CMOS）器件在p型硅衬底上的n型外延层中。 构成：在p型硅衬底（1）上生长厚的氧化物层，并且对热氧化层进行光刻工艺以限定n型掩埋层（2）。 n型掩埋层的密度根据击穿电压进行控制。 将磷离子注入到n型掩埋层中并在氧化气氛中扩散，从而生长磷掺杂的n型外延层。 形成n阱和p阱，其中进行高温热处理工艺以使n型掩埋层的结外扩散到栅电极的下部。 隔离沟槽装置。 p体结形成为沟槽栅DMOS的沟道区。 定义场氧化物层区域并控制场阈值电压。 生长氧化物层。 生长高压LDMOS和CMOS器件的栅极氧化层，并且控制阈值电压以形成栅电极。 形成LDD结，形成侧壁氧化物层（17）。 CMOS和LDMOS沟槽栅极DMOS器件的源极和漏极被连接并形成金属互连。
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公开(公告)号：KR1020010048716A
公开(公告)日：2001-06-15
申请号：KR1019990053515
申请日：1999-11-29
Applicant: 한국전자통신연구원
IPC: H01L27/085
CPC classification number: H01L29/7813 , H01L29/0847 , H01L29/42368
Abstract: PURPOSE: A method for manufacturing a trench gate power device using a self-aligned technology is provided to form a trench double diffused metal-oxide-semiconductor(TDMOS) power device by using only three masks wherein a trench sidewall layer and a self-aligned technique are utilized. CONSTITUTION: After an oxide layer and a nitride layer are sequentially grown on a silicon substrate, impurity ions are implanted by using the first mask to form a channel layer of a device. After a sidewall oxide layer and a trench are sequentially formed on the resultant structure, the sidewall oxide layer is eliminated to implant impurity ions into the bottom surface of the trench and into the region where the sidewall layer is eliminated. A gate oxide layer is grown on the surface of the trench. Polycrystalline silicon is filled inside the trench by using the second mask to form a gate electrode. An oxide layer is deposited on the trench, and an etch-back process is performed until the nitride layer is exposed. The nitride layer is removed. Impurity ions are implanted to form a body contact by using a self-aligned technology. An electrode for forming a terminal is formed on the resultant structure by using the third mask.
Abstract translation: 目的：提供一种使用自对准技术制造沟槽栅极功率器件的方法，以通过仅使用三个掩模形成沟槽双扩散金属氧化物半导体（TDMOS）功率器件，其中沟槽侧壁层和自对准 技术被利用。 构成：在硅衬底上依次生长氧化物层和氮化物层之后，通过使用第一掩模注入杂质离子以形成器件的沟道层。 在所得结构上顺序地形成侧壁氧化物层和沟槽之后，消除侧壁氧化物层，以将杂质离子注入到沟槽的底表面中，并进入去除侧壁层的区域。 栅极氧化层生长在沟槽表面上。 通过使用第二掩模将多晶硅填充在沟槽内部以形成栅电极。 在沟槽上沉积氧化物层，并且进行回蚀处理直至暴露氮化物层。 去除氮化物层。 通过使用自对准技术植入杂质离子以形成身体接触。 通过使用第三掩模，在所得结构上形成用于形成端子的电极。
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