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公开(公告)号：KR1020120032897A
公开(公告)日：2012-04-06
申请号：KR1020100094451
申请日：2010-09-29
Applicant: 한국전자통신연구원 , 안동대학교 산학협력단
IPC: G06T7/00
CPC classification number: G06K9/3241 , G06K9/4642 , G06K9/6256
Abstract: PURPOSE: A method for detecting an entity and a system thereof are provided to perform an entity detection algorithm in the remaining areas excluding the area in which a target detection object does not exist. CONSTITUTION: An image is inputted to an entity detection system(S410). The entity detection system extracts a search area for the image(S420). When the search area has been extracted, the entity detection system extracts feature data from the image(S430). After extracting the feature data, the entity detection system finally detects an entity through a boosting classifier based model such as Adaboost algorithm, and so on(S440).
Abstract translation: 目的：提供一种用于检测实体的方法及其系统，以在除了目标检测对象不存在的区域之外的剩余区域中执行实体检测算法。 构成：将图像输入到实体检测系统（S410）。 实体检测系统提取图像的搜索区域（S420）。 当提取搜索区域时，实体检测系统从图像中提取特征数据（S430）。 提取特征数据后，实体检测系统最终通过基于提升分类器的Adaboost算法等进行实体检测（S440）。
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公开(公告)号：KR100960148B1
公开(公告)日：2010-05-27
申请号：KR1020080042497
申请日：2008-05-07
Applicant: 한국전자통신연구원
CPC classification number: G06F9/3001 , G06F9/30189 , G06F9/3802 , G06F9/3885
Abstract: 데이터 프로세싱 회로는, 동작 제어 신호 및 메모리 제어 신호를 출력하는 제어 유닛과, 각각이 상기 메모리 제어 신호에 응답해서 명령을 출력하는 복수의 프로그램 메모리들, 그리고 각각이 상기 동작 제어 신호에 응답해서 상기 복수의 프로그램 메모리들로부터의 명령들 중 어느 하나를 선택적으로 수행하는 연산기들을 포함하여 동작 환경에 따라서 유연하게 동작 모드 변환이 가능하다.
Abstract translation: 数据处理电路包括：控制单元，用于输出操作控制信号和存储器控制信号;多个程序存储器，每个用于响应于存储器控制信号输出命令; 以及一个操作单元，用于有选择地从多个程序存储器的程序存储器中执行任何一个指令。
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公开(公告)号：KR100959136B1
公开(公告)日：2010-05-25
申请号：KR1020080069127
申请日：2008-07-16
Applicant: 한국전자통신연구원
CPC classification number: G06F13/28
Abstract: 본 발명에 따른 직접 메모리 접근 제어기는: 복수의 직접 메모리 접근 채널들을 각각 갖는 복수의 채널 그룹들; 및 채널 그룹 단위로 직접 메모리 접근 채널들의 활성화를 제어하는 채널 그룹 제어기를 포함하되, 상기 채널 그룹 제어기는 데이터 전송시 상기 복수의 채널 그룹들 중 적어도 하나의 채널 그룹의 직접 메모리 접근 채널을 활성화시키는 것을 특징으로 한다.
DMAC, 그룹, 채널 활성화, 대용량-
公开(公告)号：KR1020100008575A
公开(公告)日：2010-01-26
申请号：KR1020080069127
申请日：2008-07-16
Applicant: 한국전자통신연구원
CPC classification number: G06F13/28
Abstract: PURPOSE: A direct memory access controller and a data transmitting method of direct memory access channel are provided to transmit bulk block data by controlling multiple DMA channels. CONSTITUTION: A plurality of channel groups(220,230) have a plurality of DMA channels. The channel group controller(210) controls the activation of DMA channels to the channel group unit. The channel group controller activates the DMA channel of one or more channel groups in data transmission among a plurality of channel groups. The DMA channels of access channels offer the dual-port interface. The DMA channels are physically independent.
Abstract translation: 目的：提供直接存储器访问控制器和直接存储器访问通道的数据传输方法，通过控制多个DMA通道来传输批量块数据。 构成：多个通道组（220,230）具有多个DMA通道。 信道组控制器（210）控制对信道组单元的DMA信道的激活。 信道组控制器在多个信道组之间的数据传输中激活一个或多个信道组的DMA信道。 接入通道的DMA通道提供双端口接口。 DMA通道在物理上是独立的。
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公开(公告)号：KR1020090116511A
公开(公告)日：2009-11-11
申请号：KR1020080042497
申请日：2008-05-07
Applicant: 한국전자통신연구원
CPC classification number: G06F9/3001 , G06F9/30189 , G06F9/3802 , G06F9/3885
Abstract: PURPOSE: A data processing circuit is provided to convert efficiently an operating mode according to the operating environment by implementing a multi-mode of a parallel processing. CONSTITUTION: A control unit(110) outputs the operating control signal and memory control signal. Program memories(121-123) output a command in response to the memory control signal. Computing units(131-133) respond to the operating control signal and selectively perform one command among the program memories. The operating control signal outputted from the control unit includes SIMD mode signal and memory selection control signal on SIMD(Single Instruction stream Multiple Data stream) mode.
Abstract translation: 目的：提供数据处理电路，通过实现并行处理的多模式，根据操作环境有效地转换操作模式。 构成：控制单元（110）输出操作控制信号和存储器控制信号。 程序存储器（121-123）响应于存储器控制信号输出命令。 计算单元（131-133）响应于操作控制信号，并且在程序存储器中选择性地执行一个命令。 从控制单元输出的操作控制信号包括SIMD（单指令流多数据流）模式下的SIMD模式信号和存储器选择控制信号。
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Patent Agency Ranking
公开(公告)号：KR1020090065274A
公开(公告)日：2009-06-22
申请号：KR1020070132760
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: G06F15/78
Abstract: A reconfigurable SoC(System on Chip) system and a method of implementing the same are provided to perform dynamic reconfiguration by operating based on the automatic sensing of an IP necessary for the reconfiguration of an SoC. A flash memory(130) stores plural IPs(Internet Protocols), and an intrinsic code detecting unit(120) detects the intrinsic code of an IP called from a system software(110). A reconfigurable SoC(140) has a processor. The reconfigurable SoC unit configures an SoC by reading out an IP corresponding to the sensed intrinsic code.
Abstract translation: 提供了可重新配置的SoC（片上系统）系统及其实现方法，以通过基于对SoC的重新配置所需的IP的自动感测进行操作来执行动态重新配置。 闪存（130）存储多个IP（互联网协议），并且内部代码检测单元（120）检测从系统软件（110）调用的IP的固有代码。 可重新配置的SoC（140）具有处理器。 可重新配置的SoC单元通过读出对应于感测到的内在代码的IP来配置SoC。
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公开(公告)号：KR1020080102940A
公开(公告)日：2008-11-26
申请号：KR1020070115825
申请日：2007-11-14
Applicant: 한국전자통신연구원
CPC classification number: G06T15/005 , G06T2210/52
Abstract: A 3D graphic geometric transformation method using a parallel processor is provided to support a parallel process of a 3D graphic geometric transformation process by using the parallel processor, thereby simultaneously performing a lot of 3D graphic process operations effectively without an additional 3D accelerator. Model conversion and projection conversion with regard to vertex vectors of the first group are performed by using a parallel processor(210). Model conversion and projection conversion with regard to vertex vectors of the second group are performed while a value for correcting the number of employees with regard to the vertex vectors of the first group is calculated by using a universal processor(220). A value for correcting the number of employees with regard to the vertex vectors of the second group is calculated by using the universal processor while the correction of the number of employees with regard to the vertex vectors of the first group and picture mapping are simultaneously performed(230). The correction of the number of employees and picture mapping are performed with regard to the vertex vectors of the second group(240).
Abstract translation: 提供使用并行处理器的3D图形几何变换方法，以通过使用并行处理器来支持3D图形几何变换处理的并行处理，从而有效地同时执行大量3D图形处理操作而不需要额外的3D加速器。 通过使用并行处理器（210）来执行关于第一组的顶点向量的模型转换和投影转换。 执行关于第二组的顶点向量的模型转换和投影转换，同时通过使用通用处理器（220）来计算用于校正关于第一组的顶点向量的雇员人数的值。 通过使用通用处理器来计算关于第二组的顶点向量的员工数量的修正值，同时对第一组和图像映射的顶点向量的员工人数进行校正（ 230）。 对第二组（240）的顶点向量执行员工人数的修正和画面映射。
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公开(公告)号：KR1020080052225A
公开(公告)日：2008-06-11
申请号：KR1020070054320
申请日：2007-06-04
Applicant: 한국전자통신연구원
IPC: H03K19/094
CPC classification number: H03K3/356147 , H03K3/012 , H03K3/356156
Abstract: A low power clock gating circuit is provided to realize a high speed and low power by using a low threshold voltage device and a high threshold voltage device, respectively. A low power clock gating circuit(450) comprises PMOS transistors and NMOS transistors. The PMOS transistors are electrically connected between a power terminal and a first inverter(402), between the power terminal and a second inverter(422), and between the power terminal and an end gate(444), respectively. The PMOS transistors are controlled by a sleep controlling signal applied through a sleep controlling terminal and have a high threshold voltage. The NMOS transistors are electrically connected between a ground and the first inverter, between the ground and the second inverter, and between the ground and the end gate, respectively. The NMOS transistors are controlled by the sleep controlling signal and have a high threshold voltage.
Abstract translation: 提供了一种低功率时钟选通电路，通过分别使用低阈值电压器件和高阈值电压器件来实现高速和低功耗。 低功率时钟选通电路（450）包括PMOS晶体管和NMOS晶体管。 PMOS晶体管分别电连接在电源端子和第一逆变器（402）之间，电源端子与第二反相器（422）之间，以及电源端子与端口（444）之间。 PMOS晶体管由通过睡眠控制端子施加的睡眠控制信号控制并且具有高阈值电压。 NMOS晶体管分别电连接在接地和第一反相器之间，接地与第二反相器之间，以及地与端口之间。 NMOS晶体管由睡眠控制信号控制并具有高阈值电压。
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公开(公告)号：KR101920489B1
公开(公告)日：2018-11-20
申请号：KR1020170106294
申请日：2017-08-22
Applicant: 한국전자통신연구원
Abstract: 복조기로부터출력된심볼에대해디-인터리빙을수행하는디-인터리버, 디-인터리버에서출력되는비트를미리결정된나누어저장하는버퍼, 그리고버퍼에저장된비트열의예비비트가비트열의앞부분및 뒷부분에위치할수 있도록, 미리결정된개수의비트만큼비트열을순환이동시키고, 순환이동된비트열에대해비터비복호를수행하는복호부를포함하는비터비복호기가제공된다.
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公开(公告)号：KR101729976B1
公开(公告)日：2017-04-25
申请号：KR1020110055762
申请日：2011-06-09
Applicant: 한국전자통신연구원
CPC classification number: G06K9/6239 , G06K9/6269
Abstract: 본발명에따른영상인식장치는입력영상으로부터입력벡터를추출하는입력벡터추출부, 입력벡터를프로젝션벡터를사용하여압축벡터로변환하는압축벡터변환부, 훈련벡터를입력받고, 훈련벡터의폴딩연산을통해획득한프로젝션벡터를사용하여훈련파라미터를생성하는훈련파라미터생성부, 및압축벡터를훈련파라미터를사용한영상분류를통해영상인식데이터를출력하는영상분류부를포함한다.
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