公开(公告)号：FR2802705A1

公开(公告)日：2001-06-22

申请号：FR9915902

申请日：1999-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  DUTARTRE DIDIER

IPC: H01L21/20 ,  H01L21/762 ,  H01L29/06 ,  H01L21/3213 ,  B82B1/00 ,  B82B3/00

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

公开(公告)号：FR2784501A1

公开(公告)日：2000-04-14

申请号：FR9812755

申请日：1998-10-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065

Abstract: Forming a deposit of silicon by vapor phase epitaxy on silicon substrate having zones containing high concentration dopants including boron, and avoiding self-doping of the epitaxial layer with boron, comprises introducing chlorinated gas to etch the substrate within a thickness below 100 nm, before forming the epitaxial layer while the substrate is held at high temperature.

公开(公告)号：FR2783093A1

公开(公告)日：2000-03-10

申请号：FR9811221

申请日：1998-09-04

Applicant: ST MICROELECTRONICS SA

Inventor： DELPECH PHILIPPE ,  ROBILLIART ETIENNE ,  DUTARTRE DIDIER

IPC: H01L21/02 ,  H01L29/92

Abstract: Built-in capacitance (C1) on a silicon substrate (7) comprises a first highly doped polysilicon electrode (1), a thin layer (3) of silicon oxide, a second polysilicon electrode (10) and a silicide layer (4) over the second electrode. The second electrode has a high dopant concentration at the interface with the silicon oxide and a relatively low dopant concentration at the interface with the silicide layer. An Independent claim is also included for an integrated circuit, comprising at least one capacitance as above.

公开(公告)号：FR3027731B1

公开(公告)日：2018-01-05

申请号：FR1460236

申请日：2014-10-24

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER

IPC: H01L27/146 ,  H01L31/0248

公开(公告)号：DE69916699T2

公开(公告)日：2005-04-07

申请号：DE69916699

申请日：1999-05-18

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/225 ,  H01L21/205 ,  H01L21/22 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06

公开(公告)号：DE69821560T2

公开(公告)日：2005-01-05

申请号：DE69821560

申请日：1998-07-28

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: C30B29/06 ,  C23C16/24 ,  C30B25/02 ,  C30B25/20 ,  H01L21/205

Abstract: In a process for gas phase epitaxial deposition of silicon on a silicon substrate having doped zones of high arsenic concentration, self-doping of the epitaxial layer with arsenic is avoided by (a) carrying out a first thin epitaxial deposition (t5-t6) and subsequent anneal (t6-t3) under conditions and for a time such that the arsenic diffusion length is much less than the deposited layer thickness; and (b) carrying out a second epitaxial deposition (t3-t4) to achieve the desired layer thickness. Preferably, step (a) is carried out at 1100 degrees C for a time to achieve 40-60 nm thickness and step (b) is carried out at 1050 degrees C.

公开(公告)号：DE69821560D1

公开(公告)日：2004-03-18

申请号：DE69821560

申请日：1998-07-28

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: C30B29/06 ,  C23C16/24 ,  C30B25/02 ,  C30B25/20 ,  H01L21/205

Abstract: In a process for gas phase epitaxial deposition of silicon on a silicon substrate having doped zones of high arsenic concentration, self-doping of the epitaxial layer with arsenic is avoided by (a) carrying out a first thin epitaxial deposition (t5-t6) and subsequent anneal (t6-t3) under conditions and for a time such that the arsenic diffusion length is much less than the deposited layer thickness; and (b) carrying out a second epitaxial deposition (t3-t4) to achieve the desired layer thickness. Preferably, step (a) is carried out at 1100 degrees C for a time to achieve 40-60 nm thickness and step (b) is carried out at 1050 degrees C.

公开(公告)号：FR2839388A1

公开(公告)日：2003-11-07

申请号：FR0205539

申请日：2002-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： MONFRAY STEPHANE ,  DUTARTRE DIDIER ,  BOEUF FREDERIC

IPC: H01S5/34 ,  H01L33/00 ,  H01L21/336 ,  H04L9/00

Abstract: An integrated circuit, incorporating a semiconductor device forming the source of a single photon, comprises on a silicon substrate (SB): (a) a MOS transistor (TR) having a grid in the shape of a mushroom, capable of delivering on its drain, in a controlled manner, a single electron in response to a control voltage applied on its grid; (b) at least one compatible silicon quantum box (BQ), electrically coupled to the drain region (D) of the transistor, and capable of emitting a single photon on the reception of a single electron emitted by the transistor. Independent claims are also included for: (a) a cryptographic device incorporating this integrated circuit; (b) a method for the fabrication of this integrated circuit; (c) a method for the emission of a single photon using this integrated circuit.

公开(公告)号：FR2806831B1

公开(公告)日：2003-09-19

申请号：FR0003845

申请日：2000-03-27

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  DUTARTRE DIDIER ,  BAUDRY HELENE

IPC: H01L21/331 ,  H01L29/737

Abstract: A method for the fabrication of a bipolar transistor consists of forming, using non-selective epitaxy, a semiconductor region with a silicon-germanium heterojunction (1) extending over an active region (ZA) of a semiconductor substrate and an insulating region (STI) delimiting the active region, and incorporating the region of the intrinsic base of the transistor; an emitter region (8) situated above the active region and coming into contact with the upper surface of the heterojunction semiconductor region (1); a layer of polysilicon (30) forming the region of the extrinsic base of the transistor, situated either side of the emitter region (8) and separated from the heterojunction semiconductor region by a separation layer incorporating an electrical liaison conductor (74) part situated in the external neighbourhood of the emitter region, this liaison part assuring an electrical contact between the extrinsic base and the intrinsic base. An Independent claim is included for such a bipolar transistor.

公开(公告)号：FR2784501B1

公开(公告)日：2003-01-31

申请号：FR9812755

申请日：1998-10-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065

Abstract: Forming a deposit of silicon by vapor phase epitaxy on silicon substrate having zones containing high concentration dopants including boron, and avoiding self-doping of the epitaxial layer with boron, comprises introducing chlorinated gas to etch the substrate within a thickness below 100 nm, before forming the epitaxial layer while the substrate is held at high temperature.