公开(公告)号：US20020042214A1

公开(公告)日：2002-04-11

申请号：US09853279

申请日：2001-05-11

Inventor： Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

IPC: H05K001/00 ,  H01R012/00 ,  H05K003/36

CPC classification number: H05K1/141 ,  G06F1/189 ,  H05K1/0263 ,  H05K3/325 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09345 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.

公开(公告)号：US20020034088A1

公开(公告)日：2002-03-21

申请号：US09882708

申请日：2001-06-15

Inventor： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

IPC: H02M001/00

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

Abstract translation: 用于电源模块的直流母线具有与负直流导体总线板平行的正直流导体母线板。 一个或多个正极引线连接到正极母线，并且可连接到电源的正极端子。 一个或多个负极引线连接到负母线并且可连接到电源的负极端子。 DC总线具有一个或多个正极连接，可从正极母线固定到电源模块的高侧。 DC总线还具有一个或多个从负母线固定到电源模块的低端的负极连接。 正母线和负母线允许电流逆流，从而消除磁场及其相关的电感，正负母线可连接到电源模块的中心部分。

公开(公告)号：US06265672B1

公开(公告)日：2001-07-24

申请号：US09274290

申请日：1999-03-22

Applicant: Jae Suk Eum ,  Young Han Kim

Inventor： Jae Suk Eum ,  Young Han Kim

IPC: H05K103

CPC classification number: H05K1/0216 ,  H05K9/0039 ,  H05K2201/09327 ,  H05K2201/09345

Abstract: A printed circuit board having multiple layers, includes: a copper film for removing signal interference and noise and matching impedance, formed between pads of a lowermost layer which are connected to of an uppermost layer.

Abstract translation: 具有多层的印刷电路板包括：铜膜，用于消除信号干扰和噪声以及匹配阻抗，形成在最下层的焊盘之间，该最下层的焊盘与最上层连接。

公开(公告)号：US6157250A

公开(公告)日：2000-12-05

申请号：US360072

申请日：1999-07-23

Applicant: Sergio D. Camerlo

Inventor： Sergio D. Camerlo

IPC: G06F1/10 ,  H05K1/02 ,  H01L25/00

CPC classification number: H05K1/0233 ,  G06F1/10 ,  H05K1/0231 ,  H05K1/0215 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Abstract translation: 描述了简单地实际上没有成本，并且仅使用标准时钟驱动器和简单，便宜的电气部件来大大降低时钟数字电路中的时序不确定性的方法和装置。 该方法包括通过控制时钟偏移和时钟抖动来最小化时序不确定性的步骤。 通过将多行时钟的输出结合在布置在印刷电路板（PCB）上的电容金属岛上来消除本征时钟偏移。 通过使用匹配长度的宽的相对较高电容的迹线来控制外部时钟偏移，并且布置在PCB的单个公共信号层上，每个通向各自的接收器电路并且相同地终止。 通过电气隔离PCB的区域来控制时钟抖动，将时钟驱动器设置在该区域中以使噪声最小化，并向该区域提供安静的局部电源和接地。

公开(公告)号：US6052012A

公开(公告)日：2000-04-18

申请号：US106823

申请日：1998-06-29

Applicant: Sergio D. Camerlo

Inventor： Sergio D. Camerlo

IPC: G06F1/10 ,  H05K1/02 ,  G06F1/04

CPC classification number: H05K1/0233 ,  G06F1/10 ,  H05K1/0231 ,  H05K1/0215 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Abstract translation: 描述了简单地实际上没有成本，并且仅使用标准时钟驱动器和简单，便宜的电气部件来大大降低时钟数字电路中的时序不确定性的方法和装置。 该方法包括通过控制时钟偏移和时钟抖动来最小化时序不确定性的步骤。 通过将多行时钟的输出结合在布置在印刷电路板（PCB）上的电容金属岛上来消除本征时钟偏移。 通过使用匹配长度的宽的相对较高电容的迹线来控制外部时钟偏移，并且布置在PCB的单个公共信号层上，每个通向相应的接收器电路并且相同地终止。 通过电气隔离PCB的区域来控制时钟抖动，将时钟驱动器设置在该区域中以使噪声最小化，并向该区域提供安静的局部电源和接地。

公开(公告)号：US5912597A

公开(公告)日：1999-06-15

申请号：US413908

申请日：1995-03-30

Applicant: Hideho Inagawa ,  Tomoyasu Arakawa ,  Toru Otaki ,  Yasushi Takeuchi ,  Yoshimi Terayama ,  Toru Osaka

Inventor： Hideho Inagawa ,  Tomoyasu Arakawa ,  Toru Otaki ,  Yasushi Takeuchi ,  Yoshimi Terayama ,  Toru Osaka

IPC: H05K1/00 ,  H05K1/02 ,  H03H1/00

CPC classification number: H05K1/0216 ,  H05K1/0289 ,  H05K2201/09236 ,  H05K2201/09345 ,  H05K2201/09727 ,  H05K2201/10689

Abstract: A printed circuit board capable of suppressing radiation noise efficiently includes a first conductive layer where a plurality of power lines are provided at predetermined spacing along one direction, a second conductive layer where a plurality of power lines are provided at predetermined spacing along a direction orthogonal to the one direction, and a plurality of plated through holes for connecting the power lines on the first conductive layer and the power lines on the second conductive layer at the overlapping points of those lines. The power lines contain thin lines and thick lines spaced between a plurality of the thin lines. The predetermined spacing is determined based on a rising time or falling time of the output signal of the IC to be mounted on the circuit board.

Abstract translation: 能够有效地抑制辐射噪声的印刷电路板包括沿着一个方向以预定间隔设置多条电源线的第一导电层，沿着与...正交的方向以预定间隔设置多条电源线的第二导电层 一个方向，以及多个用于连接第一导电层上的电力线和第二导电层上的电力线的电镀通孔。 电力线包含在多条细线之间间隔的细线和粗线。 基于要安装在电路板上的IC的输出信号的上升时间或下降时间确定预定间隔。

公开(公告)号：US3832602A

公开(公告)日：1974-08-27

申请号：US28444972

申请日：1972-08-28

Applicant: SIEMENS AG

Inventor： SCHAFF U ,  KAISER W ,  ENGELHARD D ,  HOFMANN H

IPC: H05K1/02 ,  H05K5/00

CPC classification number: H05K1/0233 ,  H05K1/0215 ,  H05K1/0227 ,  H05K1/0231 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09663 ,  H05K2201/09972 ,  H05K2201/1006 ,  H05K2201/10166

Abstract: A print for control modules of contact-free control and regulating systems comprising an insulating carrier plate having one portion of one surface adjacent the control inputs provided with a plurality of anti-interference filters. The number of filters is the same as the number of control inputs. The other portion of the one surface of the plate is provided with the same number of threshold value stages connected to the filters. The other surface of the carrier plate has a metal layer thereon which is electrically interrupted in accordance with the boundary between the first and second portions of the one surface thereof. The portion of the layer corresponding to the first portion is connected to ground and the portion of the layer corresponding to the second portion is connected to a reference potential.

Abstract translation: 一种无接触式控制和调节系统的控制模块的打印件，包括绝缘载板，该绝缘载板具有与设置有多个抗干扰滤波器的控制输入相邻的一个表面的一部分。 滤波器的数量与控制输入的数量相同。 板的一个表面的另一部分设置有连接到过滤器的相同数量的阈值级。 载体板的另一个表面上具有金属层，该金属层根据其一个表面的第一和第二部分之间的边界被电中断。 对应于第一部分的层的部分连接到地面，并且对应于第二部分的层的部分连接到参考电位。

公开(公告)号：EP3306792A1

公开(公告)日：2018-04-11

申请号：EP15894081.7

申请日：2015-05-29

Applicant: Shindengen Electric Manufacturing Co., Ltd.

Inventor： SASAKI, Mitsumasa

IPC: H02K11/00

CPC classification number: H05K1/0224 ,  H02K11/00 ,  H02K11/33 ,  H02P25/16 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0008 ,  H05K5/0026 ,  H05K2201/09027 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09354 ,  H05K2201/1009 ,  H05K2201/10166 ,  H05K2201/10287 ,  H05K2201/1034 ,  H05K2201/10522

Abstract: A semiconductor device of the present invention includes: a substrate (12) that is annular or partially annular; a first phase control circuit (14) provided on the substrate (12), the first phase control circuit being configured to control a first phase of a plurality of phases of a motor; a second phase control circuit (15) provided on the substrate (12) so as to be adjacent to the first phase control circuit (14) in a circumferential direction of the substrate (12), the second phase control circuit (15) being configured to control a second phase of the plurality of phases of the motor, the second phase being different from the first phase; a power supply wiring (18) disposed on one of an outer circumferential side and an inner circumferential side of the first phase control circuit (14) and the second phase control circuit (15) in a radial direction of the substrate (12), the power supply wiring (18) being connected to the first phase control circuit (14) and the second phase control circuit (15), and the power supply wiring (18) extending in the circumferential direction of the substrate (12); and a ground winding (19) disposed on an other one of the outer circumferential side and the inner circumferential side of the first phase control circuit (14) and the second phase control circuit (15) in the radial direction of the substrate (12), the ground winding (19) being connected to the first phase control circuit (14) and the second phase control circuit (15), and the ground winding (19) extending in the circumferential direction of the substrate (12).

Abstract translation: 本发明的半导体器件包括：基板（12），其为环形或部分环形; 设置在所述基板（12）上的第一相位控制电路（14），所述第一相位控制电路被配置为控制电动机的多个相的第一相; 第二相位控制电路（15），其设置在所述基板（12）上，以便在所述基板（12）的圆周方向上与所述第一相位控制电路（14）相邻;所述第二相位控制电路 以控制所述电动机的所述多个相的第二相，所述第二相与所述第一相不同; 在所述第一相位控制电路（14）和所述第二相位控制电路（15）的所述基板（12）的半径方向的外周侧和内周侧中的一方设置的电源布线（18），所述 电源布线（18）连接到第一相位控制电路（14）和第二相位控制电路（15），电源布线（18）沿基板（12）的圆周方向延伸。 以及设置在所述第一相位控制电路（14）和所述第二相位控制电路（15）的所述基板（12）的径向外周侧和内周侧中的另一方上的接地绕组（19） ，接地绕组（19）连接到第一相位控制电路（14）和第二相位控制电路（15），接地绕组（19）沿基板（12）的圆周方向延伸。

公开(公告)号：EP3133906A1

公开(公告)日：2017-02-22

申请号：EP15779477.7

申请日：2015-04-09

Applicant: Nidec Sankyo Corporation

Inventor： GOMI, Kazuhiro ,  KURIBAYASHI, Ikuro

IPC: H05K3/46 ,  G06F21/86 ,  G06K7/00

CPC classification number: G06F21/86 ,  G06K7/00 ,  G06K7/087 ,  G06K7/10009 ,  H05K1/0219 ,  H05K1/0275 ,  H05K2201/09345

Abstract: Provided is a printed circuit board having a breakdown detection pattern formed thereon for preventing illicit acquisition of sensitive data, the printed circuit board being configured so that false detection of a disconnection or a short in the breakdown detection pattern can be prevented. The printed circuit board (7) comprises a breakdown detection pattern layer (32) wherein a breakdown detection pattern is formed for detecting a disconnection and/or a shorting thereof, a first pattern layer (31) disposed more to a Y1 direction side than the breakdown detection pattern layer (32), a second pattern layer (33) disposed more to a Y2 direction side than the breakdown detection pattern layer (32), and signal pattern layers (34 to 36) disposed more to the Y2 direction side than the second pattern layer (33). Formed in the first pattern layer (31) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y1 direction side. Formed in the second pattern layer (33) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y2 direction side.

Abstract translation: 提供了一种印刷电路板，其上形成有用于防止非法获取敏感数据的击穿检测图案，印刷电路板被配置为可以防止故障检测图案的断线或短路错误检测。 印刷电路板（7）包括击穿检测图案层（32），其中形成用于检测断开和/或短路的击穿检测图案，第一图案层（31）比Y1方向侧更多地设置 击穿检测图案层（32），比击穿检测图案层（32）更多地设置在Y2方向侧的第二图案层（33）以及比Y2方向侧更多配置的信号图案层（34〜36） 第二图案层（33）。 形成在第一图案层（31）中的是从Y1方向侧覆盖击穿检测图案的接地图案和电源图案。 形成在第二图案层（33）中的是从Y2方向侧覆盖击穿检测图案的接地图案和电源图案。

公开(公告)号：EP2690935A1

公开(公告)日：2014-01-29

申请号：EP13177340.0

申请日：2013-07-22

Applicant: Zumtobel Lighting GmbH

Inventor： Block, Steffen

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0295 ,  H05K1/111 ,  H05K2201/09345 ,  H05K2201/10106 ,  H05K2201/10189 ,  H05K2201/10522 ,  Y02P70/611

Abstract: Leiterplatte (11, 22) zum Bestücken mit Leuchtkörpern, insbesondere LEDs (15, 16), mit mindestens einem Bestückungsbereich (1/2, 2/2, 1/6-6/6), wobei der Bestückungsbereich (1/2, 2/2, 1/6-6/6) mindestens zwei Anschlussmöglichkeiten (2) für Leuchtkörper (15) aufweist, welche an voneinander getrennt ansteuerbare Kanäle (Ch1-Ch4) angeschlossen sind und wobei innerhalb des Bestückungsbereichs (1/2, 2/2, 1/6-6/6) einer der mindestens zwei Anschlussmöglichkeiten (2) eine zusätzliche Anschlussmöglichkeit (14) für einen Leuchtkörper (16) zugeordnet ist, wobei die Anschlussmöglichkeit (2) und die der Anschlussmöglichkeit (2) zugeordnete zusätzliche Anschlussmöglichkeit (14) an den gleichen Kanal (Ch3) angeschlossen sind.

Abstract translation: 板（11）具有包括用于灯体的两个连接单元（2）的组装区域（1/2,2/2），即LED，其中连接单元被连接在彼此分开控制的通道（Ch1-Ch4）处 。 用于灯体的附加连接单元（14）直接邻近两个连接单元中的一个连接，并且与组装区域内的两个连接单元中的一个连接。 两个连接单元和相关联的附加连接单元中的一个连接在相同的通道中的一个上。