公开(公告)号：JPH07297819A

公开(公告)日：1995-11-10

申请号：JP7300594

申请日：1994-04-12

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN EMU ATARA ,  DABURIYUU DEERU HOPUKINZU

IPC: G09C1/00 ,  H04L9/06 ,  H04L9/10 ,  H04L9/14 ,  H04L9/32

Abstract: PURPOSE: To improve reliability in a message from node to node by using one session key for encrypting a personal identification number(PIN) together with a message authentication code(MAC), random number, message and continuous numbers. CONSTITUTION: When a user inputs his own PIN 37 at a starting node 31, the PIN is transformed into a block, together with additional data bits and the PIN of reference bit length is formed. Furthermore, transaction data or a message 41 is linked with continuous numbers 43. These linked message and continuous numbers are encrypted by an ordinary DES module 45 by the PIN and one field 53 in these data is operated as a MAC. The field 53 of selected MAC is encrypted by an ordinary encryption module 55 together with the random number, while using a session key K1 as an encryption key 50. Moreover, a PIN 39 is encrypted by a DES encryption module 60, while using the session key K1 as the encryption key 50.

公开(公告)号：JPH0713789A

公开(公告)日：1995-01-17

申请号：JP5448394

申请日：1994-02-28

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  CHIYAARUZU II PIITO JIYUNIA ,  DAGURASU II JIYUUETSUTO ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To check the state of each CPU by the other CPU in the case of providing a fault tolerant type computer system. CONSTITUTION: The fault tolerant type computer system is provided with the plural CPU for executing the same instruction stream and a common memory having a memory space to be accessed by all the CPU. Inside the common memory, private memory spaces 155a, 155b and 155c are respectively provided for storing state information for each CPU. Each private memory space enables write only from one CPU corresponding to that space but read is enabled from all the CPU. Thus, it can be immediately and easily evaluated whether the state of its own CPU is equal with the states of the other CPU or not.

公开(公告)号：JPH06301528A

公开(公告)日：1994-10-28

申请号：JP3481694

申请日：1994-03-04

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU TEII FURAA

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38 ,  G06F11/30

Abstract: PURPOSE: To enable a digital device which becomes a subsystem to achieve a timer function when the condition of a branch microinstruction does not appear. CONSTITUTION: This digital device is provided with an address register 32 which is connected to a storage device 30 so that the register 32 can operate in accordance with instructions successively accessed from the device 30 to test whether or not a condition signal appears within a prescribed period of time and operates in first and second modes and the register 32 performs access to instructions from the device by sequentially generating address signals in the first mode and measures the prescribed period of time in the second mode. The register 32 is provided with an incrementing means 50 which increments a holding value and a means 60 which generates a time-out signal when no condition signal exists within the prescribed period of time.

公开(公告)号：JPH05334237A

公开(公告)日：1993-12-17

申请号：JP1881493

申请日：1993-02-05

Applicant: TANDEM COMPUTERS INC

Inventor： ARUBAATO RUI ,  UIRIAMU TEI FURAA

IPC: G01D21/00 ,  G06F11/30 ,  G06F11/34 ,  G06F13/36

Abstract: PURPOSE: To provide a device for monitoring the environment of a remote component connected to a host processor by using a standard interface bus having a limited number of address ports and its method. CONSTITUTION: A host adapter 3 contains a bus repeater 4 and a monitoring logic section 5. The section 5 has a bus interface section 8 selectably connected to an interface bus 2 and a host processor 1, a control section 9, and an environment monitoring section 10. The bus repeater 4 has a host interface transceiver 6 connected to the host processor 1 through the interface bus 2 and a drive interface transceiver 7 connected to a storage device 13 through an interface bus 20. The transceivers 6 and 7 are connected to the control section 9 through control lines 11 and 12, respectively.

公开(公告)号：JPH0535930A

公开(公告)日：1993-02-12

申请号：JP33823791

申请日：1991-12-20

Applicant: TANDEM COMPUTERS INC

Inventor： BENJIYAMIN SHIEERUMAN

IPC: G06K17/00 ,  G06K7/00 ,  G06K7/08

Abstract: PURPOSE: To make simultaneous reading-out/writing possible by holding a data recording card at a fixed position and moving a magnetic reading-out/writing head to bring a contact head into contact simultaneously with an IC data recording medium. CONSTITUTION: The data card 3 is fixed between a magnetic head 41 and a head 21. The presence of the data card 3 is detected by a switch 35. The switch sends a signal to a CPU 8 which starts feed data transfer sequence. The CPU 8 urges a user to input necessary transaction data on a keyboard 2 via a display device 4. The communication with a remote site along a communication circuit 6 is executable. The data transfer between the data card 3 and the CPU 8 is started when the signal is sent to a motor 49 which in turn moves the magnetic head 41 along the magnetic strip 7. Simultaneously, the CPU 8 receives the data from an IC by the head 21. Interaction with the data of both stored on the magnetic strip 7 and the IC is thus made possible.

公开(公告)号：JPH04273506A

公开(公告)日：1992-09-29

申请号：JP25209991

申请日：1991-09-30

Applicant: TANDEM COMPUTERS INC

Inventor： RENAADO II OOBUAAHAUSU ,  DANIERU II RENOSUKII

IPC: G06F1/06 ,  G06F1/12 ,  G06F13/36 ,  G06F13/42 ,  G06F15/78

Abstract: PURPOSE: To provide a synchronous processor unit which performs the communication between its two divided parts which are clocked at different frequency levels after connecting both parts together via a buffer unit. CONSTITUTION: The synchronous processor 102 is divided into two parts and clocked by the different clock signals. A part 12 including an instruction execution unit 20 and an instruction and data memory 24 is clocked by the frequency of a higher level. On the other hand, the other part 14 of the processor 102 including the processor elements which are not frequently used is clocked by the frequency of a lower level. The elements of both parts 12 and 14 are connected together via the individual data buses and also selectively connected to each other via a buffer unit 62. The signal generated by a clock signal generation unit 70 also monitors the instructions that are carried out by the unit 20. When the communication is performed between the parts 12 and 14, the clocks of high and low speeds are synchronized with each other and the buses of both parts are connected together via the unit 62.

公开(公告)号：JPH03230222A

公开(公告)日：1991-10-14

申请号：JP32516190

申请日：1990-11-27

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  MAIZANUA EMU RAAMAN ,  RICHIYAADO HARISU

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28

Abstract: PURPOSE: To perform 2-cycle RAM access without sacrificing performance by using the first and second banks of a control memory and storing micro- instructions. CONSTITUTION: A calculation system 10 is provided with a macroinstruction processor (IPU) 14 for storing and taking out macroinstructions, this micro- instruction sequencer 22 for generating the micro-instructions corresponding to the macro-instructions stored inside the IPU 14 and a data processor (DPU) 26 for storing and processing data corresponding to instructions from the IPU 14 and the micro-instruction sequencer 22. Then, the micro-instruction sequencer 22 communicates with the IPU 14 and the DPU 26 respectively through an IPU-sequencer bus 30 and a DPU-sequencer bus 36. Also, the IPU 14 communicates with the DPU 26 through an IPU-DPU bus 37. Thus, the DPU 26 starts the execution of the micro-instruction at a rank 1 while a first micro- instruction is executed at the rank 2.

公开(公告)号：JPH03116233A

公开(公告)日：1991-05-17

申请号：JP13513790

申请日：1990-05-24

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO

IPC: G06F9/26 ,  G06F9/38

Abstract: PURPOSE: To improve an instruction processing capability by transmitting the family of instructions including an instruction in the format of collation to an ALU and a memory in one clock. CONSTITUTION: First and second instructions in an instruction family are stored in pipe line registers ROF and ROS 20 and 18, decoded by decoders 22 and 24, and the decoded results are outputted to DCO buses 28 and 30. Then, status information from the both decoded results is transmitted to a pairing logical devices PLU control port 26 on status buses 32 and 34. This is used for a processor which uses one stack as the data source and data sink of the ALU (arithmetic and logical unit) processing. Thus, a capability can be improved by the parallel processing capability of the instruction family of this system.

公开(公告)号：JPH0334641A

公开(公告)日：1991-02-14

申请号：JP5977190

申请日：1990-03-09

Applicant: TANDEM COMPUTERS INC

Inventor： MAACHIN EMU ATARA ,  UEBUSUTAA DEE HOPUKINSU ,  RARUFU AARU BESUTOTSUKU ,  JIEE YANGU KIMU

IPC: G09C1/00 ,  G07F7/10 ,  H04L9/08 ,  H04L9/06 ,  H04L9/14

Abstract: PURPOSE: To make it impossible to discover an encryption key by monitoring a transaction with time by using a cryptography for generating a unique key. CONSTITUTION: A unique dynamic encryption key is periodically generated related with each of plural remote terminals by using the seed key of a system which is present only in a host computer. The generated dynamic encryption key is used at the time of enciphering data transferred to a host computer by a terminal, and also used for decoding data received from the host computer. This method includes the storage of the dynamic key preliminarily generated by the host computer related with a terminal in the terminal. Thus, it is impossible to discover the encipherment key by monitoring a transaction with time.

公开(公告)号：JPH02202636A

公开(公告)日：1990-08-10

申请号：JP32246189

申请日：1989-12-11

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  RANDARU JII BANTON ,  DAGURASU II JIYUUETSUTO ,  PIITAA SHII NOOUTSUDO ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO TABURIYUU HOOSUTO

IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To replace faulty parts without system shutdown by minimizing a porting circuit to separate faulty parts while running the system. CONSTITUTION: When all CPUs 11 to 13 enter the interrupt state, they output the interrupt requests to all memory modules 14 and 15 by individual lines of an interrupt bus 35. When all interrupts are ported, memory modules 14 and 15 transmit the interrupt requests ported to three CPUs 11 to 13 through the bus 35. CPUS 11 to 13 synchronize these ported interrupts with a CPU interrupt signal through an inter-CPU bus 18, and interrupts are indicated to all CPUs 11 to 13 at a common point of an instruction stream.