LIQUID SUPPLYING DEVICE
    71.
    发明专利

    公开(公告)号:JPH11304571A

    公开(公告)日:1999-11-05

    申请号:JP1005099

    申请日:1999-01-19

    Abstract: PROBLEM TO BE SOLVED: To enable the accurate monitoring of the amount of remaining liquid by detecting a liquid level in a liquid container with a liquid level sensor and generating a signal at the time that the liquid level comes down to a predetermined residual level. SOLUTION: A chemical solution 21 such as a chemical reaction agent is stored in a liquid container 20, and its liquid level is detected by a liquid level sensor 27 including an amplifying unit 22 to amplify a detection signal and a fiber photoelectric sensor 23. The chemical solution 21 is flowed out via a capillary tube 25 and is supplied for a spin-on-glass station. The liquid level comes down with the use of the chemical solution 21. At the time when the chemical solution 21 comes down to the tip 26 of the fiber photoelectric sensor 23, a predetermined amount of the solution remains in the liquid container 20. At this time, a signal is generated by the fiber photoelectric sensor 23, is amplified by the amplifying unit 22, and is transmitted to an alarm 28. By this, it becomes possible for a user of the spin-on glass station to know the appropriate timing of filling or exchange of the chemical solution 21.

    NOZZLE POT OF SPIN OF GLASS(SOG) COATING MACHINE

    公开(公告)号:JPH11290753A

    公开(公告)日:1999-10-26

    申请号:JP14924498

    申请日:1998-05-29

    Abstract: PROBLEM TO BE SOLVED: To decrease the time required for detaching and attaching works by forming a nozzle pot in such a manner that the wide opening of the nozzle is used to accept a fluid from a pot, a narrow opening is attached to the end of the projection of the nozzle to be inserted into a duct, and that a fluid is supplied to the outside through the wide and narrow openings and the duct. SOLUTION: A nozzle pot to spray a fluid on a wafer mounted on a spin-on- glass coating machine consists of a pot 20 to house the fluid, a funnel nozzle 21 having a wide opening 22, a narrow opening 23a and a projection 23b, and an attaching device 200 to attach the nozzle 21. The wide opening 22 of the nozzle 21 attached with the attaching device 200 is connected to the pot 20 and is used to accept the fluid from the pot 20. The narrow opening 23a of the nozzle 21 is formed at the end of the projection 23b so as to supply the chemical fluid in the pot 20 to the outside through a duct 24. Thereby, detaching and attaching works can be carried out in a short time.

    ETCHING METHOD OF SILICON NITRIDE
    73.
    发明专利

    公开(公告)号:JPH11283964A

    公开(公告)日:1999-10-15

    申请号:JP13949398

    申请日:1998-05-21

    Abstract: PROBLEM TO BE SOLVED: To reduce CD bias, without affecting a gate oxide layer by eliminating a silicon nitride layer through anisotropic plasma etching with a mixture of tetrafluoromethane, argon, and nitrogen, with a photoresist layer as a mask. SOLUTION: On a field oxide layer 301, a gate oxide layer 302, polysilicon layers 303, 303a, and metal silicide layers 304, 304a are formed sequentially. A photoresist layer is formed in conformity with the polysilicon layer 303, 303a formed on the silicon nitride layer, covering part of the silicon nitride layer, The exposed part of the silicon nitride layer is eliminated by anisotropic plasma etching. Here, a mixture of tetrafluoromethane, argon, and nitrogen is used as an etching reactant. After removing the photoresist layer, a cap silicon nitride layer 305, 305a and a polymer layer 306, 306a are sequentially formed on the metal silicide layer 304, 304a.

    DUAL DAMASCENE TECHNIQUE
    74.
    发明专利

    公开(公告)号:JPH11186274A

    公开(公告)日:1999-07-09

    申请号:JP13531598

    申请日:1998-05-18

    Abstract: PROBLEM TO BE SOLVED: To provide a dual damascene technique which is capable of preventing etching damages and making a change small in critical dimensions. SOLUTION: A first and a second photoresist layer are each previously formed in the prescribed regions of a narrow opening and a wide opening of a dual damascene. A composite layer 37 composed of an HSQ(hydrogen silsesquioxane) layer 34 and an oxide layer 36 provided on the layer 34 is formed surrounding the first and second photoresist layer respectively. After the photoresist layers are removed, the left opening 42 is filled up with an adhesive/barrier layer and a metal layer 40.

    POLISHING HEAD RETAINING RING OF CHEMICAL-MECHANICAL POLISHING MACHINE

    公开(公告)号:JPH1190819A

    公开(公告)日:1999-04-06

    申请号:JP31313697

    申请日:1997-11-14

    Abstract: PROBLEM TO BE SOLVED: To provide a polishing head retaining ring for CMP(chemical- mechanical polishing) device with which the slurry coated in the CMP process can be distributed uniformly over the surface of a wafer polished by the polishing head. SOLUTION: A head retaining ring 40 is designed for use in a CMP device equipped with a polishing table, polishing pad, polishing head to hold a semiconductor wafer held in a fixed position, and a means to coat a constant amount of slurry to the wafer, wherein the head includes an air compressing means to apply an air pressure to a wafer loader used to hold the wafer in the specified position. This ring 40 is constructed so as to have a plurality of linear grooves 42 arranged at an approx. constant angular spacing, and the grooves 42 are inclined in the radial direction so as to form an acute angle of attack to the slurry existing outside the ring when it rotates.

    PLANARIZATION TECHNIQUE FOR DRAM CELL CAPACITOR ELECTRODE

    公开(公告)号:JPH10321814A

    公开(公告)日:1998-12-04

    申请号:JP12124297

    申请日:1997-05-12

    Inventor: SON SEII YU SUIYO

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM forming method which enables high productivity and high reliability. SOLUTION: A silicon nitride etch stopping layer 90 is bonded onto an entire structure of a device, including first and second source/drain regions 80 and 84 which have been exposed during a spacer etch process, followed by further bonding of a thick oxide layer 96 thereon. By performing chemicomechanical polishing, the surface of the thick oxide layer 96 is planarized. An opening is formed in the thick oxide layer 96 above the first source/drain region 84 so as to be stopped by the etch stopping layer 90. Thereafter, the etch stopping layer 90 within the opening of the thick oxide layer 96 is removed to form a capacitor electrode 98 therein, so as to be in contact with the exposed portion of the first source/drain region 84. Similarly, a bit line contact for the device may be formed.

    ERROR CORRECTING METHOD FOR CONTROLLER FOR LARGE CAPACITY STORAGE DEVICE AND ERROR DETECTING METHOD THEREFOR

    公开(公告)号:JPH10301722A

    公开(公告)日:1998-11-13

    申请号:JP10494297

    申请日:1997-04-22

    Inventor: SO SHOTOKU

    Abstract: PROBLEM TO BE SOLVED: To speedily transfer data from a CD-ROM storage device including error correction. SOLUTION: Data read from a storage disk 50 are transmitted to both a buffer memory 66 and an error detecting circuit in parallel as a serial data stream. This error detecting method is constituted of a step for dividing the segment of the serial data stream corresponding to a data block by a polynomial for error inspection, and a step for deciding a remainder calculated by this division. When any error is not detected, data stored in the buffer memory 66 are transferred to a data bus in a host computer, and when an error is detected, error correction is continued until the remainder is reduced to zero, and the data are transferred.

    SEMICONDUCTOR CIRCUIT AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

    公开(公告)号:JPH10256543A

    公开(公告)日:1998-09-25

    申请号:JP5918697

    申请日:1997-03-13

    Abstract: PROBLEM TO BE SOLVED: To form a low-resistivity silicide structure to obtain adequate silicide electrode structure by forming a conductive material layer laterally extending over both side walls of a polysilicon structure. SOLUTION: A device is produced by depositing a polysilicon structure, forming openings through a layer by the photolithography, dipping it in a dil. HF soln. to laterally etch an intermediate Si oxide layer to form undercuts, thermally growing a gate electrode layer 56, depositing polysilicon into the undercut regions by the chemical vapor deposition to form polysilicon structures 58, 60, heavily implanting ions vertically in a substrate 10 with protrusions used for a mask to self-align heavily doped regions at the protrusions, depositing a thin Ti layer by the physical evaporation, quickly heat annealing at a high enough temp. to form Ti silicide regions 74.

    METHOD OF FORMING INTERCONNECTION STRUCTURE IN SEMICONDUCTOR DEVICE

    公开(公告)号:JPH10242272A

    公开(公告)日:1998-09-11

    申请号:JP18140797

    申请日:1997-07-07

    Inventor: SON SEII

    Abstract: PROBLEM TO BE SOLVED: To form a metal interconnection structure having a resistivity at a uniform and predictable level by providing a conductive layer adjacent a first insulation layer on a semiconductor substrate and depositing an etching stopper layer different from the first insulation layer on the top surfaces of the conductive layer and first insulation layer. SOLUTION: The method comprises forming a metal wiring 32 having an upper surface substantially coplanar to the surface of a dielectric layer 30, forming an etching stopper layer 34 to cover the device surface and exposure regions on the surfaces of a first level metal wiring layer 32 and dielectric layer 30, depositing an intermetallic dielectric layer 36 on the stopper layer 34, forming vias through the dielectric layer 36, etching the vias, depositing a glue layer 40 to cover the dielectric layer 36 surface and vias, forming metal plugs 42 in the vias to contact the layer 40, thereby forming a metal interconnection structure having a resistivity at a uniform and predictable level.

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