公开(公告)号：KR100456697B1

公开(公告)日：2004-11-10

申请号：KR1020020044986

申请日：2002-07-30

Applicant: 삼성전자주식회사

Inventor： 김홍기 ,  강호규 ,  박문한 ,  윤명근 ,  원석준 ,  정용국 ,  김경훈

IPC: H01L27/02

CPC classification number: H01L27/10852 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.

Abstract translation: 电容器包括通过物理气相沉积和化学气相沉积形成的上电极。 电容器的上电极可以包括通过化学气相沉积形成的第一上电极和通过物理气相沉积形成的第二上电极。 或者，上电极可以包括通过物理气相沉积形成的第一上电极和通过化学气相沉积形成的第二上电极。 电容器的上电极通过使用化学气相沉积和物理气相沉积的两个步骤形成。 因此，上电极可以很厚且迅速形成，由此上电极的电特性不会劣化。

公开(公告)号：KR1020040047461A

公开(公告)日：2004-06-05

申请号：KR1020020075693

申请日：2002-11-30

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  윤명근 ,  원석준 ,  권대진

IPC: H01L21/8242

CPC classification number: H01L27/10852 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/31637 ,  H01L27/10817 ,  H01L28/40 ,  H01L28/56 ,  H01L28/90

Abstract: PURPOSE: A method for simplifying the process for forming a dielectric layer and fabricating a capacitor of a semiconductor device is provided to simplify the fabricating process and maintain the same electrical characteristic as a conventional process by depositing a dielectric layer while using only a source gas and by performing a curing process only once. CONSTITUTION: The first electrode is formed on a semiconductor substrate(S10). The first dielectric layer is deposited on the first electrode(S20). The first dielectric layer is cured in an oxygen-containing atmosphere(S30). The second dielectric layer is formed on the cured first dielectric layer by using only source gas without using reaction gas(S40). The second electrode is formed on the second dielectric layer without a curing process performed on the second dielectric layer(S50).

Abstract translation: 目的：提供一种用于简化用于形成电介质层的工艺和制造半导体器件的电容器的方法，以简化制造工艺，并且通过在仅使用源气体的同时沉积介电层来保持与常规工艺相同的电特性， 通过仅进行一次固化处理。 构成：第一电极形成在半导体衬底上（S10）。 第一电介质层沉积在第一电极上（S20）。 第一电介质层在含氧气氛中固化（S30）。 通过仅使用源气体而不使用反应气体，在固化的第一电介质层上形成第二电介质层（S40）。 第二电极形成在第二电介质层上，而不在第二电介质层上进行固化处理（S50）。

公开(公告)号：KR100408410B1

公开(公告)日：2003-12-06

申请号：KR1020010030529

申请日：2001-05-31

Applicant: 삼성전자주식회사

Inventor： 주재현 ,  김완돈 ,  유차영 ,  정용국

IPC: H01L27/108

CPC classification number: H01L28/60 ,  H01L27/10855 ,  H01L28/91

Abstract: In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

Abstract translation: 在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，衬底中具有暴露衬底的孔。 电容器的整体下电极设置在基板上并具有设置在孔中的接触插塞部分。 电介质层位于下电极上并且电容器的上电极位于电介质层上。 在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，衬底中具有暴露衬底的孔。 阻挡层设置在衬底的暴露部分上和层间绝缘层的侧壁上。 接触插塞设置在阻挡层上的孔中。 电容器的下电极设置在接触插塞上并且在它们之间的边界处与接触插塞接合。 电介质层位于下电极上并且电容器的上电极位于电介质层上。

公开(公告)号：KR1020020091663A

公开(公告)日：2002-12-06

申请号：KR1020010030529

申请日：2001-05-31

Applicant: 삼성전자주식회사

Inventor： 주재현 ,  김완돈 ,  유차영 ,  정용국

IPC: H01L27/108

CPC classification number: H01L28/60 ,  H01L27/10855 ,  H01L28/91

Abstract: PURPOSE: A semiconductor device having an MIM(Metal-Insulator-Metal) capacitor and a method for fabricating the same are provided to form a contact plug without a seam by preventing formation of cracks on an interlayer dielectric. CONSTITUTION: An interlayer dielectric(103) having a contact hole(105) is formed on a semiconductor substrate(101). A barrier(107) is formed on an inner wall and a bottom of the contact hole(105). A contact plug(119a) is formed in the contact hole(105). A lower electrode(119b) of a capacitor is formed on the contact plug(119a). The contact plug(119a) and the lower electrode(119b) are formed with one body. A lower mold layer pattern(111a) and a wet etch prevention layer pattern(113a) are formed on an upper face of the interlayer dielectric(103) and both sides of the lower electrode(119b). A dielectric layer(121) is formed on the lower electrode(119b). An upper electrode(123) is formed on the dielectric layer(121).

Abstract translation: 目的：提供具有MIM（金属 - 绝缘体 - 金属）电容器的半导体器件及其制造方法，以通过防止在层间电介质上形成裂纹而形成不具有接缝的接触插塞。 构成：在半导体衬底（101）上形成具有接触孔（105）的层间电介质（103）。 在所述接触孔（105）的内壁和底部形成有阻挡层（107）。 接触插头（119a）形成在接触孔（105）中。 电容器的下电极（119b）形成在接触插塞（119a）上。 接触插头（119a）和下电极（119b）形成有一个主体。 在层间电介质（103）的上表面和下电极（119b）的两侧形成下模层图案（111a）和湿蚀刻防止层图案（113a）。 在下电极（119b）上形成介电层（121）。 在电介质层（121）上形成上电极（123）。

公开(公告)号：KR101908288B1

公开(公告)日：2018-10-16

申请号：KR1020120049216

申请日：2012-05-09

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  채승호 ,  허정식

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66477 ,  H01L29/6656 ,  H01L29/6659

Abstract: 반도체소자및 이를제조하는방법을제공한다. 반도체소자는, 기판상에배치되는제1 절연막, 제1 절연막상에배치되는게이트전극및 게이트전극및 제1 절연막상에배치되며, 제1 방전사이트(discharge site)를포함하는제2 절연막을포함한다.

公开(公告)号：KR101847629B1

公开(公告)日：2018-04-10

申请号：KR1020120013807

申请日：2012-02-10

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  박상욱 ,  최민희

IPC: H01L21/318 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/78

CPC classification number: H01L29/7831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823807 ,  H01L21/8258 ,  H01L23/291 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 반도체소자가제공된다. 본발명의일 실시예에따른반도체소자는, 기판; 기판상에위치하고, 게이트절연층및 게이트전극층을포함하는게이트구조물; 기판및 게이트구조물상에위치하고, 실리콘을포함하는제1 질화막; 및제1 질화막상에위치하고, 제1 질화막보다낮은실리콘원자분율을가지는제2 질화막을포함한다.

公开(公告)号：KR101811713B1

公开(公告)日：2017-12-22

申请号：KR1020110071559

申请日：2011-07-19

Applicant: 삼성전자주식회사 ,  엔엑스피 유에스에이, 인코포레이티드 ,  글로벌파운드리즈 싱가포르 피티이 엘티디 ,  인터내셔널 비즈니스 머신즈 코오퍼레이션

Inventor： 정용국 ,  강래구 ,  김남성 ,  양대원

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/28255 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7843

Abstract: 반도체장치의제조방법이제공된다. 반도체장치의제조방법은, SiGe 채널영역을포함하는 PMOS 트랜지스터를형성하고, 상기 PMOS 트랜지스터의적어도일부를수소플라즈마에노출하고, 상기 PMOS 트랜지스터상에인장스트레스막을형성하는것을포함한다.

Abstract translation: 提供了一种制造半导体器件的方法。 一种用于制造半导体器件的方法，包括PMOS晶体管，其包括SiGe沟道区域的形成，并至少暴露所述PMOS晶体管的氢等离子体的一部分，以及形成在PMOS晶体管的拉伸应力膜。

公开(公告)号：KR101599725B1

公开(公告)日：2016-03-07

申请号：KR1020090022780

申请日：2009-03-17

Applicant: 삼성전자주식회사 ,  인피니언 테크놀로지스 아게 ,  인터내셔널 비즈니스 머신즈 코오퍼레이션

Inventor： 정용국 ,  서봉석 ,  유동희 ,  권오성 ,  권오정 ,  김성동

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833

Abstract: 본발명의실시예에따른집적회로장치를제조하는방법은반도체기판내에 P형소스/드레인영역을갖는 PMOS 트랜지스터를형성하고, 그후 상기소스/드레인영역상에확산배리어막을형성하는것을포함한다. 실리콘질화막은상기소스/드레인영역의반대편으로연장되는적어도일부의상기확산배리어막상에증착된다. 상기실리콘질화막을자외선조사(UV radiation)에노출시켜상기증착된실리콘질화막으로부터수소를제거한다. 상기수소의제거는전계효과트랜지스터의채널영역내에인장응력(tensile stress)을증가시키는데작용할수 있다. 상기자외선조사단계후, 상기소스/드레인영역을노출시키기위해상기제1 그리고제2 실리콘질화막을패터닝(patterning)하는단계와실리사이드콘택층(contact layers)을상기노출된소스/드레인영역의바로위(directly on)에형성하는단계가뒤 따른다.

公开(公告)号：KR1020120076084A

公开(公告)日：2012-07-09

申请号：KR1020100138077

申请日：2010-12-29

Applicant: 삼성전자주식회사

Inventor： 정용국

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823462 ,  H01L28/57

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to control a threshold voltage of a transistor to be increased by forming an oxygen trapping film on the upper side of a gate electrode and an active area. CONSTITUTION: An element isolation film limiting an active area(5) is formed on a substrate(1). A gate electrode(9) is formed on the active area. A gate insulating layer(7) is formed between the gate electrode and the active area. A spacer(11) is formed on the side of the gate electrode. An oxygen trapping film(15a) is formed on the substrate which includes the gate electrode. An inter-layer insulating film(17) is formed on the oxygen trapping film. A contact etching stop film is formed between the oxygen trapping film and the inter-layer insulating film.

Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过在栅极电极和有源区域的上侧形成氧捕获膜来控制晶体管的阈值电压增加。 构成：在衬底（1）上形成限制有源区（5）的元件隔离膜。 在有源区上形成栅电极（9）。 在栅电极和有源区之间形成栅极绝缘层（7）。 在栅电极侧形成间隔物（11）。 在包括栅电极的基板上形成氧捕获膜（15a）。 在氧捕获膜上形成层间绝缘膜（17）。 在氧捕获膜和层间绝缘膜之间形成接触蚀刻停止膜。

公开(公告)号：KR1020080012691A

公开(公告)日：2008-02-12

申请号：KR1020060073912

申请日：2006-08-04

Applicant: 삼성전자주식회사

Inventor： 정용국 ,  김태범 ,  신동석

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/76801 ,  H01L21/76829

Abstract: A method for fabricating a semiconductor integrated circuit device is provided to prevent moisture or external ions from penetrating the inside of a first interlayer dielectric by forming a contact in the first interlayer dielectric covering NMOS and PMOS transistors and by dehydrogenating the first interlayer dielectric. An NMOS transistor(100) is formed on a semiconductor substrate(10). A first interlayer dielectric(320) with predetermined stress is formed on the NMOS transistor. A contact(328) connected to the NMOS transistor is formed in the first interlayer dielectric. The first interlayer dielectric is dehydrogenated to vary the stress. A capping layer is formed on the first interlayer dielectric by an in-situ method to prevent moisture or external ions from penetrating the first interlayer dielectric.

Abstract translation: 提供一种制造半导体集成电路器件的方法，以通过在覆盖NMOS和PMOS晶体管的第一层间电介质中形成接触并通过使第一层间电介质脱氢来防止水分或外部离子穿透第一层间电介质的内部。 在半导体衬底（10）上形成NMOS晶体管（100）。 在NMOS晶体管上形成具有预定应力的第一层间电介质（320）。 连接到NMOS晶体管的触点（328）形成在第一层间电介质中。 将第一层间电介质脱氢以改变应力。 通过原位方法在第一层间电介质上形成覆盖层，以防止水分或外部离子穿透第一层间电介质。