公开(公告)号：KR100471377B1

公开(公告)日：2005-03-11

申请号：KR1020020072344

申请日：2002-11-20

Applicant: 한국전자통신연구원

Inventor： 정광효 ,  고종수 ,  윤현철 ,  양해식 ,  표현봉 ,  김성진 ,  신용범 ,  김윤태

IPC: C12Q1/00

Abstract: 본 발명은 표면장력으로 제어되는 미세유체소자에 관한 것으로, 상부 기판 및 하부 기판이 결합되어 유체를 제어하고 반응시키는 미세유체소자에 있어서, 하부 기판은, 제1 유체 및 제2 유체가 각각 저장되는 제1 저장 챔버 및 제2 저장 챔버와, 제1 저장 챔버 및 제2 저장 챔버와 연결되는 감지 챔버와, 제1 유체 또는 제2 유체의 이동을 정지시키는 제1 유동 정지부 및 제2 유동 정지부와, 제1 유체 또는 제2 유체의 이동 속도를 감소시키는 유동 지연부와, 반응이 완료된 제1 유체 또는 제2 유체가 폐기되는 폐기 챔버 및 유체가 이동되도록 유동 지연부와 폐기 챔버 사이를 연결하는 유로를 포함하고, 상부 기판은 감지 챔버 내의 생화학반응을 측정하는 감지부를 포함하며, 제1 유체가 모세관 힘에 의해 감지 챔버로 이동하여 1차 생화학 반응이 일어나고, 소정 시간 경과 후 제2 유체가 모세관 힘에 의해 감지 챔버로 유입되면 제1 유체의 교체 및 2 차 생화학반응이 일어나는 것을 특징으로 한다. 따라서, 추가적인 장치 및 전원공급이 필요 없게 되어, 장치의 소형화, 휴대화가 가능하고, 제조비를 낮춤과 동시에 제조 수율을 높일 수 있을 뿐만 아니라, 사용 시 고장이 거의 없는 효과가 있다.

公开(公告)号：KR1020040039571A

公开(公告)日：2004-05-12

申请号：KR1020020067683

申请日：2002-11-02

Applicant: 한국전자통신연구원

Inventor： 김성진 ,  신용범 ,  양해식 ,  박세호 ,  이대식 ,  윤태환 ,  김규원 ,  김윤태

IPC: B01F5/06

Abstract: PURPOSE: A microfluidic device applied to a biochip is provided to mix microfluid by disposing hot wires in a reaction chamber to form layers and heating or cooling stored fluids. CONSTITUTION: The microfluidic device for mixing microfluid comprises a first flow channel delivering a first fluid(106); a second flow channel delivering a second fluid(108); a reaction chamber connected to ends of the first and second flow channels and having hot wires(104) for heating the inside; and a part for stopping flow connected to end of the reaction chamber so as to prevent the first and second fluids from moving. When the first and second fluids meet in the reaction chamber and form layers, the first and second fluids are heated or cooled using the hot wires to generate the density difference, thereby mixing the first and second fluids by gravity.

Abstract translation: 目的：提供应用于生物芯片的微流体装置，通过在反应室中设置热丝以形成层并加热或冷却储存的流体来混合微流体。 构成：用于混合微流体的微流体装置包括：输送第一流体（106）的第一流动通道; 输送第二流体（108）的第二流动通道; 反应室连接到第一和第二流动通道的端部，并具有用于加热内部的热丝（104） 以及用于停止与反应室的端部连通的流动的部件，以防止第一和第二流体移动。 当第一和第二流体在反应室中相交并形成层时，使用热丝将第一和第二流体加热或冷却，以产生密度差，从而通过重力混合第一和第二流体。

公开(公告)号：KR1020040035104A

公开(公告)日：2004-04-29

申请号：KR1020020063838

申请日：2002-10-18

Applicant: 한국전자통신연구원

Inventor： 윤태환 ,  양해식 ,  이대식 ,  박세호 ,  신용범 ,  김규원 ,  김성진 ,  김윤태

IPC: C12Q1/68

Abstract: PURPOSE: A fluorescence detecting device for detecting biomolecule using amorphous-silicon thin film transistor and a method for detecting the fluorescence using the same are provided, thereby reducing the size and costs of DNA chip because optical devices are not used, and requiring no fluorescence stimulating light blocking filter by using a transparent substrate. CONSTITUTION: A fluorescence detecting device for detecting biomolecule using amorphous-silicon thin film transistor comprises a first substrate with a probe biomolecule; a transparent substrate(102) having a first domain(I), a second domain(II) and a third domain(III), and having a first surface(102a) where a light is irradiated and a second surface(102b) arranged to face the first substrate; a light thin film transistor(TFToptic) producing electric charge responding to the fluorescence produced from the biomolecule on the second surface(102b) and positioned in the first domain(I); a capacity(CAP) storing the electric charge produced from the light thin film transistor(TFToptic) and positioned in parallel to the light thin film transistor(TFToptic) in the second domain(II); and a transfer thin film transistor(TFTtrans) transferring the electric charge to an additional analysis system and positioned in parallel to the capacity(CAP) in the third domain(III).

Abstract translation: 目的：提供一种用于使用非晶硅薄膜晶体管检测生物分子的荧光检测装置和使用其的荧光检测方法，从而由于不使用光学器件而不需要荧光刺激而降低DNA芯片的尺寸和成本 遮光过滤器采用透明基板。 构成：使用非晶硅薄膜晶体管检测生物分子的荧光检测装置，包括具有探针生物分子的第一基底; 具有第一结构域（I），第二结构域（II）和第三结构域（III）的透明基板（102），并且具有照射光的第一表面（102a）和第二表面（102b） 面对第一衬底; 产生电荷的光薄膜晶体管（TFToptic），产生响应于由第二表面（102b）上的生物分子产生并位于第一域（I）中的荧光的电荷; 存储从所述光薄膜晶体管（TFT光电）产生并与所述第二域（II）中的所述薄膜晶体管（TFToptic）并行定位的电荷的容量（CAP）; 和转移薄膜晶体管（TFTtrans），其将电荷转移到另外的分析系统并且与第三域（III）中的容量（CAP）平行放置。

公开(公告)号：KR100423721B1

公开(公告)日：2004-03-22

申请号：KR1020010062698

申请日：2001-10-11

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  김성진 ,  백규하 ,  이희태 ,  이상균 ,  박성수

IPC: C25D17/06

Abstract: PURPOSE: A plating apparatus having electrode ring is provided to form a plating film having a uniformed thickness by adhering the electrode ring to the upper end of a plating tank so that an electric field is uniformly distributed on the surface of wafers during electroplating. CONSTITUTION: The plating apparatus comprises a plating tank; a plural first polarity contact point rods and a second polarity contact point rod formed on the plating tank; a loop shaped electrode ring(200) which is connected to the plural first polarity contact point rods, and on the inner surface of which a plurality of stepped projections(220) are formed so that the bodies to be plated are rested on the stepped projections with the circumference of the edge of various bodies to be plated having different size being contacted with the plurality of stepped projections(220), wherein the plating apparatus further comprises a metal box arranged at the lower part of the electrode ring to be connected to the second polarity contact point rod; and a sprayer arranged at the lower part of the metal box to spray a plating solution, wherein the plating tank comprises first plating tank on which the electrode ring and metal box are mounted, and second plating tank on which the sprayer is mounted, the first and second plating tanks are separately connected to each other, wherein the plating apparatus further comprises a plating tank of which outer wall covers the plating tank, and the upper part of which is opened, and a lid installed to open or close an opening part of the plating tank outer wall, wherein a power supply terminal connected to the first and second polarity contact point rods is installed on the lower surface of the lid, wherein the residual surface of the electrode ring is coated with a chemical resistant coating material(210) except a surface on which the bodies to be plated are rested and supported and a part of the electrode ring which comes in contact with the first polarity contact point rods, and wherein the coating material(210) is Teflon or polyethylene.

Abstract translation: 目的：提供具有电极环的电镀设备，通过将电极环粘附到电镀槽的上端以形成具有均匀厚度的电镀膜，从而在电镀期间电场均匀分布在晶片的表面上。 构成：电镀设备包括电镀槽; 形成在所述镀槽上的多个第一极性接点棒和第二极性接点棒; 一个与多个第一极性接触点杆连接的环形电极环（200），在其内表面上形成多个阶梯状突起（220），以使待电镀的物体靠在阶梯状突起 其中待镀的各种物体的边缘的周边具有与多个阶梯状突起（220）接触的不同尺寸，其中电镀装置还包括布置在电极环的下部以连接到 第二极性接触点杆; 以及布置在所述金属盒的下部以喷射电镀液的喷雾器，其中所述电镀槽包括其上安装有所述电极环和金属箱的第一电镀槽和其上安装所述喷雾器的第二电镀槽，所述第一电镀槽 以及第二电镀槽彼此分开连接，其中，所述电镀设备还包括电镀槽，所述电镀槽的外壁覆盖所述电镀槽并且其上部被打开;以及盖，其被安装以打开或关闭所述电镀槽的开口部 电镀槽外壁，其中连接到第一和第二极性接触点杆的电源端子安装在盖的下表面上，其中电极环的残留表面涂覆有耐化学腐蚀涂层材料（210） 除了待电镀的物体被搁置和支撑的表面以及与第一极性接触点杆接触的电极环的一部分之外，并且其中， 涂层材料（210）是聚四氟乙烯或聚乙烯。

公开(公告)号：KR100404319B1

公开(公告)日：2003-11-01

申请号：KR1020000083260

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김성진 ,  주철원 ,  백규하 ,  이희태 ,  박성수 ,  송민규

IPC: H01L21/60

CPC classification number: H01L2224/11 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

Abstract: 본 발명은 구리 교차오염을 방지할 수 있는 고 밀도/ 고 균일성 솔더 범프(solder bump) 형성방법에 관한 것으로서, 보다 상세하게 설명하면 고 밀도/고 균일성을 갖는 솔더 볼 형성방법 및 구리 교차오염문제의 해결방법에 관한 것이다.
상기한 문제를 해결하기 위해 본 발명은 대규모 집적회로 칩 기판위에 전기도금용 전극을 스퍼터링(sputtering)한 후, 다중코팅방법으로 감광제막 코팅을 하여 비아(via)를 형성한 다음에 솔더(solder) 도금을 위한 구리 씨드(Cu seed)를 스퍼터링(sputtering)하여 솔더 볼(solder ball)을 형성하는 것을 특징으로 하는 솔더 범프 형성방법이 제공된다.

Abstract translation: 目的：制造能够防止硅实验室中铜交叉污染的焊料凸块的方法是通过充分使用常规装置来降低制造成本，从而形成高球和高密度焊球。 构成：用于电镀的电极（4）溅射在高集成电路芯片衬底（1）上。 涂覆光致抗蚀剂层以形成通孔。 用于焊接电镀的铜种子被溅射以形成焊球。 用于防止铜和焊料镀覆的铜/钛晶种在光致抗蚀剂层上被薄的溅射。 光致抗蚀剂层通过多涂层技术形成。

公开(公告)号：KR100395489B1

公开(公告)日：2003-08-25

申请号：KR1020000083173

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김성진 ,  주철원 ,  백규하 ,  박성수 ,  이희태 ,  송민규

IPC: H01L21/60

Abstract: PURPOSE: A method for fabricating a bump is provided to minimize stress generated by the difference of a thermal expansion coefficient between a chip and a substrate, by forming the bump of a high aspect ratio. CONSTITUTION: Photoresist is coated several times to form a relatively thick photoresist. An exposure and development process is selectively performed regarding the photoresist to form a plurality of vias. A bump material is plated on the via. The photoresist is stripped. The plated bump material is reflowed to a spherical bump by a reflow method.

Abstract translation: 目的：通过形成高纵横比的凸点，提供一种用于制造凸点的方法，以最小化由于芯片和衬底之间的热膨胀系数的差异而产生的应力。 构成：光致抗蚀剂被多次涂覆以形成相对厚的光致抗蚀剂。 关于光致抗蚀剂选择性地执行曝光和显影工艺以形成多个通孔。 通孔上镀有凸块材料。 光刻胶被剥离。 电镀凸点材料通过回流方法回流成球形凸点。

公开(公告)号：KR1020030065787A

公开(公告)日：2003-08-09

申请号：KR1020020005783

申请日：2002-02-01

Applicant: 한국전자통신연구원

Inventor： 이진희 ,  윤형섭 ,  이경호 ,  심재엽 ,  김성진

IPC: H01L21/336

Abstract: PURPOSE: A method of forming a T-shaped gate is provided to improve step coverage and to form a fine gate so that the cross section area of the gate can be increased and the resistance of the gate can be reduced. CONSTITUTION: The first and second insulation layer(25,26) having different etch selectivity are sequentially formed on a semiconductor substrate(21). A hole having its upper diameter is larger than its lower diameter is formed by etching the first and second insulation layer. A third insulation layer(29) is formed to bury the hole and then a portion of the semiconductor substrate is exposed. By etch back of the third insulation layer, the third insulation layer remains on the hole. The first and second photoresist layer are sequentially formed on the entire surface. The first and second photoresist layer are patterned to expose the hole though an opening. A metal layer(34a) for gate is deposited and the first and second photoresist layer are removed to form a T-shaped gate.

Abstract translation: 目的：提供一种形成T形栅极的方法，以提高台阶覆盖度并形成精细栅极，从而可以增加栅极的横截面面积，并可以减小栅极电阻。 构成：在半导体衬底（21）上依次形成具有不同蚀刻选择性的第一和第二绝缘层（25,26）。 通过蚀刻第一绝缘层和第二绝缘层形成其上部直径大于其下部直径的孔。 形成第三绝缘层（29）以埋置孔，然后露出半导体衬底的一部分。 通过第三绝缘层的回蚀刻，第三绝缘层保留在孔上。 第一和第二光致抗蚀剂层顺序地形成在整个表面上。 图案化第一和第二光致抗蚀剂层，以通过开口露出孔。 沉积用于栅极的金属层（34a），并且去除第一和第二光致抗蚀剂层以形成T形门。

公开(公告)号：KR1020020054227A

公开(公告)日：2002-07-06

申请号：KR1020000083260

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김성진 ,  주철원 ,  백규하 ,  이희태 ,  박성수 ,  송민규

IPC: H01L21/60

CPC classification number: H01L2224/11 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PURPOSE: A method for fabricating a solder bump capable of preventing copper cross contamination in a silicon laboratory is to reduce fabricating cost by sufficiently using a conventional apparatus so that a high ball and a high density solder ball are formed. CONSTITUTION: An electrode(4) for electroplating is sputtered on a high integrated circuit chip substrate(1). A photoresist layer is coated to form a via. A copper seed for solder plating is sputtered to form the solder ball. A copper/titanium seed for preventing the copper and solder from being plated is thinly sputtered on the photoresist layer. The photoresist layer is thickly formed by a multi-coating technology.

Abstract translation: 目的：制造能够防止硅实验室中的铜交叉污染的焊料凸块的方法是通过充分使用常规装置来降低制造成本，从而形成高球和高密度焊球。 构成：用于电镀的电极（4）溅射在高集成电路芯片衬底（1）上。 涂覆光致抗蚀剂层以形成通孔。 用于焊接电镀的铜种子被溅射以形成焊球。 用于防止铜和焊料电镀的铜/钛晶种在光致抗蚀剂层上被薄的溅射。 光致抗蚀剂层通过多涂层技术形成。