Abstract:
본 발명은 입사광을 특정 셀에 조사하여 DNA 등의 생체분자 혹은 고분자 어레이를 형성하기 위한 투과형 프로그래머블 마스크 및 이를 이용한 생체분자 혹은 고분자 어레이를 형성 방법에 관한 것이다. 프로그래머블 마스크의 단위 화소들 각각은 입사광의 진행을 방해하고 전기 영동에 의해 이동하는 전하를 띤 입자들을 구비하는 용액과 입자들의 배열을 변화시켜 입사광의 투과도를 조절하기 위해서, 입자들에 전압을 인가하기 위한 전극들을 구비하여 구성된다.
Abstract:
The present invention relates to a field emission device and a method of fabricating the same. The method includes forming a hole having a nanometer size using silicon semiconductor process and then forming an emitter within the hole to form a field emission device. Therefore, the present invention can reduce the driving voltage and thus lower the power consumption.
Abstract:
PURPOSE: An electrophoresis display by using a tube type capsule and a manufacturing method thereof are provided to implement various colors easily. CONSTITUTION: A transparent lower electrode(401) is formed on a glass substrate or a plastic substrate by using a metal or ITO(Indium Tin Oxide). Plural lower electrodes(401) are arranged to a substrate with a constant interval toward the first direction, that is, a horizontal direction. A tube type capsule(403) is manufactured and arranged on the lower electrode(401). An upper electrode(405) is formed on the tube type capsule(403) with a constant interval toward the second direction, that is, a longitudinal direction.
Abstract:
PURPOSE: A capacitor and a manufacturing method thereof are provided to be capable of increasing the effective contact surface area between an electrode layer and a dielectric layer for obtaining large charging capacity at a limited cell area. CONSTITUTION: A capacitor is provided with a substrate(102), the first electrode layer(106) formed on the substrate, and at least one conductive wire(108) formed on the first electrode layer. The capacitor further includes a dielectric layer(110) for enclosing the conductive wire and the second electrode layer(112) formed on the dielectric layer. Preferably, the conductive wire is in the shape of a pillar type structure. Preferably, the conductive wires are independently isolated from each other. Preferably, the conductive wire has a diameter of 5 nm to 10 μm and a height of 5 nm to 100 μm.
Abstract:
A method for manufacturing ultra-thin film silicon according to an embodiment of the present invention comprises the steps of preparing a silicon layer on top of a silicon oxide film; forming a thermal oxide film in the upper region of the silicon layer by performing thermal oxidation on the surface of the silicon layer and forming a first silicon layer thinner than the silicon layer in the lower region of the silicon layer; exposing the surface of the first silicon layer by removing the thermal oxide film; forming an ozone oxide film in the first silicon layer adjacent to the surface of the first silicon layer by performing ozone surface oxidation on the surface of the first silicon layer and forming a second silicon layer thinner than the silicon layer between the ozone oxide film and the silicon oxide film; exposing the surface of the second silicon layer by removing the ozone oxide film; and separating the second silicon layer from the silicon oxide film by etching the silicon oxide film.
Abstract:
The present invention relates to a method for forming core-shell nanoparticles for metal ink. The method for forming core-shell nanoparticles for metal ink according to one embodiment of the present invention includes a step of forming metal oxide nanoparticle cores and a step of forming core-shell nanoparticles by forming metal shells on the surface of the cores. The metal oxide nanoparticle cores comprises core-shell nanoparticles which are transparent metal oxide nanoparticles. The metal oxide nanoparticles have a particle diameter of 1-100 nm.
Abstract:
본 발명은 그래핀 박막의 증착방법에 관한 것으로, 기판에 기상의 그래핀 소스를 제공하는 단계와, 상기 그래핀 소스를 상기 기판 상에 흡착층을 형성하는 단계와, 상기 흡착층을 가열하여 상기 흡착층을 활성화하는 단계를 포함할 수 있다. 이에 따르면, 대면적의 균일한 그래핀 박막을 형성할 수 있다. 그래핀, 시간분할 급속가열, 그래핀 소스, 활성 소스
Abstract:
PURPOSE: A thin film transistor and a manufacturing method thereof are provided to increase the life time of the thin film transistor by including a gate insulation layer with a first inorganic layer, an organic layer, and a second inorganic layer. CONSTITUTION: A source electrode(SE) is arranged on a base member. A drain electrode(DE) is separated from the source electrode on a plane. An active layer partially overlaps with the source electrode and the drain electrode on the plane. A gate electrode(GE) partially overlaps with the active layer on the plane. A gate insulation layer is arranged between the active layer and the gate electrode on a vertical surface, and includes a first inorganic layer(11), an organic layer(12), and a second inorganic layer(13) which are successively laminated.