公开(公告)号：AU2002351403A1

公开(公告)日：2003-07-09

申请号：AU2002351403

申请日：2002-12-18

Applicant: INTEL CORP

Inventor： HORIGAN JOHN ,  DAI XIA ,  CLINE LESLIE ,  MITTAL MILLIND

IPC: G06F1/32 ,  G06F12/08

Abstract: In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

公开(公告)号：DE69628325D1

公开(公告)日：2003-06-26

申请号：DE69628325

申请日：1996-12-24

Applicant: INTEL CORP

Inventor： DULONG CAROLE ,  MENNEMEIER M ,  PELEG D ,  BUI H ,  KOWASHI EIICHI ,  MITTAL MILLIND ,  EITAN BENNY ,  FISHER A ,  MAYTAL BENNY

IPC: G06F7/544 ,  G06F9/302 ,  G06F7/38 ,  G06F7/52 ,  G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  G06F15/80

Abstract: A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.

公开(公告)号：HK1050255A1

公开(公告)日：2003-06-13

申请号：HK03102201

申请日：2003-03-26

Applicant: INTEL CORP

Inventor： HOWARD C HERBERT ,  GRAWROCK DAVID W ,  ELLISN CARL M ,  GOLLIVER ROGER A ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F1/00 ,  G06F12/14 ,  G06F21/00 ,  G06F

公开(公告)号：DE10196006T1

公开(公告)日：2003-04-03

申请号：DE10196006

申请日：2001-03-14

Applicant: INTEL CORP

Inventor： ELLISON CARL M ,  GOLLIVER ROGER A ,  HERBERT HOWARD C ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F21/22 ,  G06F21/00 ,  G09C1/00 ,  H04L9/08 ,  H04L9/10 ,  G06F1/00

Abstract: The present invention is a method, apparatus, and system to generate a key hierarchy for use in an isolated execution environment of a protected platform. In order to bind secrets to particular code operating in isolated execution, a key hierarchy comprising a series of symmetric keys for a standard symmetric cipher is utilized. The protected platform includes a processor that is configured in one of a normal execution mode and an isolated execution mode. A key storage stores an initial key that is unique for the platform. A cipher key creator located in the protected platform creates the hierarchy of keys based upon the initial key. The cipher key creator creates a series of symmetric cipher keys to protect the secrets of loaded software code.

公开(公告)号：GB2378794A

公开(公告)日：2003-02-19

申请号：GB0225043

申请日：2001-03-14

Applicant: INTEL CORP

Inventor： ELLISON CARL M ,  GOLLIVER ROGER A ,  HERBERT HOWARD C ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F21/22 ,  G06F21/00 ,  G09C1/00 ,  H04L9/08 ,  H04L9/10 ,  G06F1/00

Abstract: The present invention is a method, apparatus, and system to generate a key hierarchy for use in an isolated execution environment of a protected platform. In order to bind secrets to particular code operating in isolated execution, a key hierarchy comprising a series of symmetric keys for a standard symmetric cipher is utilized. The protected platform includes a processor that is configured in one of a normal execution mode and an isolated execution mode. A key storage stores an initial key that is unique for the platform. A cipher key creator located in the protected platform creates the hierarchy of keys based upon the initial key. The cipher key creator creates a series of symmetric cipher keys to protect the secrets of loaded software code.

公开(公告)号：DE69624578D1

公开(公告)日：2002-12-05

申请号：DE69624578

申请日：1996-08-07

Applicant: INTEL CORP

Inventor： PELEG D ,  MITTAL MILLIND ,  MENNEMEIER M ,  EITAN BENNY ,  DULONG CAROLE ,  KOWASHI EIICHI ,  WITT WOLF ,  LIN CHU ,  BINDAL AHMET ,  FISHER A ,  BUI H

IPC: G06F7/53 ,  G06F5/00 ,  G06F7/00 ,  G06F7/48 ,  G06F7/483 ,  G06F7/49 ,  G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305 ,  G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  G06F17/16 ,  G06T1/20 ,  G06F15/00 ,  G06F15/76 ,  G06F15/80

公开(公告)号：RU2179331C2

公开(公告)日：2002-02-10

申请号：RU98113914

申请日：1996-12-17

Applicant: INTEL CORP

Inventor： LIN DERRIK ,  VAKKALAGADDA RAMAMOKHAN R ,  GLJU EHNDRJU F ,  MENNEMEJER LEHRRI M ,  PELEG ALEKSANDER D ,  BISTRI DEHVID ,  MITTAL MILLIND ,  DJULONG KEHROL ,  KOVASI EHJITI ,  EHJTAN BENNI

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

Abstract: computer systems; execution of floating-point commands and packed data by processor. SUBSTANCE: processor unit has decoding device, set of physical registers, and display device. As an alternative, processor unit may have in addition extracting device and set of buffer registers. Method describes procedures of command execution by processor with aid of its own items. EFFECT: enlarged functional capabilities. 51 cl, 27 dwg, 2 tbl

公开(公告)号：AU4368301A

公开(公告)日：2001-10-15

申请号：AU4368301

申请日：2001-03-14

Applicant: INTEL CORP

Inventor： ELLISON CARL M ,  GOLLIVER ROGER A ,  HERBERT HOWARD C ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F21/22 ,  G06F21/00 ,  G09C1/00 ,  H04L9/08 ,  H04L9/10 ,  G06F1/00

Abstract: The present invention is a method, apparatus, and system to generate a key hierarchy for use in an isolated execution environment of a protected platform. In order to bind secrets to particular code operating in isolated execution, a key hierarchy comprising a series of symmetric keys for a standard symmetric cipher is utilized. The protected platform includes a processor that is configured in one of a normal execution mode and an isolated execution mode. A key storage stores an initial key that is unique for the platform. A cipher key creator located in the protected platform creates the hierarchy of keys based upon the initial key. The cipher key creator creates a series of symmetric cipher keys to protect the secrets of loaded software code.

公开(公告)号：CA2230108C

公开(公告)日：2000-12-12

申请号：CA2230108

申请日：1996-08-07

Applicant: INTEL CORP

Inventor： WITT WOLF ,  PELEG ALEXANDER D ,  BUI TUAN H ,  MENNEMEIER LARRY M ,  MITTAL MILLIND ,  KOWASHI EIICHI ,  BINDAL AHMET ,  FISCHER STEPHEN A ,  LIN DERRICK CHU ,  DULONG CAROLE ,  EITAN BENNY

IPC: G06F7/53 ,  G06F5/00 ,  G06F7/00 ,  G06F7/48 ,  G06F7/483 ,  G06F7/49 ,  G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305 ,  G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  G06F17/16 ,  G06T1/20 ,  G06F15/76 ,  G06F15/80

Abstract: A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first (810), second (811), third (812), and fourth multiplier (813), wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder (850) coupled to the first and second multipliers (810, 811), and second adder (851) coupled to the third and fourth multipliers (812, 813). A third storage area (871) is coupled to the adders (850, 851). The third storage area (871) includes a first and second field for saving output of the first and second adders (850, 851), respectively, as first and second data elements of a third packed data.

公开(公告)号：CA2205830C

公开(公告)日：2000-08-15

申请号：CA2205830

申请日：1995-12-01

Applicant: INTEL CORP

Inventor： YAARI YAAKOV ,  MITTAL MILLIND ,  PELEG ALEXANDER ,  EITAN BENNY ,  MENNENEIER LARRY M

IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38

Abstract: The processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.