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    71.
    发明专利
    未知

    公开(公告)号：FR2839811A1

    公开(公告)日：2003-11-21

    申请号：FR0205965

    申请日：2002-05-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  CREMER SEBASTIEN ,  MARTY MICHEL

    IPC: H01L21/02 ,  H01L23/522 ,  H01L21/334 ,  H01L29/94

    Abstract: Capacitor is manufactured in substrate (1) by digging recess into substrate; forming first conformal layer of insulating material; forming second conductive layer; forming third layer of conductive or insulating material filling up recess; digging trenches into third layer, across entire height; depositing fourth layer of conductive material; forming fifth layer of dielectric material; and depositing sixth layer of conductive material. An Independent claim is also included for a capacitor formed in a substrate comprising: (a) a recess (2) dug into a substrate; (b) a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; (c) a second layer of a conductive material covering the first layer; (d) a third layer of a conductive or insulating material filling the recess; (e) trenches crossing the third layer; (f) a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges; (g) a fifth layer of a dielectric material covering the fourth layer; and (h) a sixth layer of a conductive material covering the fifth layer.

    74.
    发明专利
    未知

    公开(公告)号：FR2799048B1

    公开(公告)日：2003-02-21

    申请号：FR9911895

    申请日：1999-09-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

    IPC: H01L29/73 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/737 ,  H01L21/00 ,  H01L21/22 ,  H01L29/732

    Abstract: Bipolar transistor fabrication includes a step of producing a base region (8) comprising an extrinsic base (800) and an intrinsic base, and a step of producing an emitter block having a narrower lower part located in an emitter-window above the intrinsic base. Production of the extrinsic base (800) involves dopant implantation after defining the emitter-window, on both sides at a determined distance from the lateral limits of the emitter-window, with self-alignment about the emitter-window, and before emitter block formation. An oxide block (13) is formed on an insulating layer located above the intrinsic base. The oxide block (13) has a narrower lower part (130) located in an etched hole of the insulating layer and whose dimensions correspond to those of the emitter-window, and an upper wider part (131) resting on the insulating layer. The lateral sides of the etched hole of the insulating layer are self-aligned with the lateral sides (FV) of the upper part of the oxide block. Ion implantation of the extrinsic base is formed on both sides of the upper part of the oxide block (13).

    75.
    发明专利
    未知

    公开(公告)号：FR2813707B1

    公开(公告)日：2002-11-29

    申请号：FR0011419

    申请日：2000-09-07

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  CHANTRE ALAIN ,  MARTY MICHEL ,  JOUAN SEBASTIEN

    IPC: H01L21/331 ,  H01L29/10 ,  H01L21/28

    Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

    76.
    发明专利
    未知

    公开(公告)号：FR2801420B1

    公开(公告)日：2002-04-12

    申请号：FR9914746

    申请日：1999-11-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

    IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L29/732

    Abstract: Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector on a layer of extrinsic collector in a semiconductor substrate; (b) making a lateral isolating region; (c) making a base next to he intrinsic collector and the lateral isolating region; and (d) making a bipartite dope emitter in situ. Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector (4) on a layer of extrinsic collector (2) in a semiconductor substrate (1); (b) making a lateral isolating region (5) surrounding the upper part of the intrinsic collector and of wells of the imprisoned extrinsic collector (60); (c) making a base (8) next to he intrinsic collector and the lateral isolating region and comprising a non-selective epitaxy of a semiconductor region (8) comprising at least one layer of silicon; (d) making a bipartite dope emitter (11) in situ comprising: (i) making a first layer (110) of the emitter formed from microcrystalline silicon and directly in contact with a part (800) of the upper surface of the semiconductor region situated on top of the intrinsic collector; and (ii) making a second part (111) of emitter from polycrystalline silicon; the two parts (110, 111) being separated by an oxide layer (112).

    77.
    发明专利
    未知

    公开(公告)号：FR2779573B1

    公开(公告)日：2001-10-26

    申请号：FR9807061

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  REGOLINI JORGE LUIS

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737 ,  H01L29/732

    Abstract: The bipolar transistor comprises a base (Be) of heterojunction silicon-germanium. The base is in block (8) of layers of silicon and silicon-germanium on an initial layer (17) of silicon nitride spread on a region with lateral isolation (5). An internal collector (4) is enclosed and situated inside a window in the layer of silicon nitride. The fabrication process includes the growth of a layer of silicon dioxide on a block of semiconductor. A layer of silicon nitride (Si3N4) is then deposited, and etched until the layer of silicon dioxide. A chemical process is used to remove a portion of the layer of silicon dioxide within the window. The layer of silicon nitride has a thickness of about 300 Angstrom, and that of silicon dioxide about 200 Angstrom.

    78.
    发明专利
    未知

    公开(公告)号：FR2805923A1

    公开(公告)日：2001-09-07

    申请号：FR0002855

    申请日：2000-03-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

    IPC: H01L21/331

    Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

    79.
    发明专利
    未知

    公开(公告)号：FR2766294A1

    公开(公告)日：1999-01-22

    申请号：FR9709164

    申请日：1997-07-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  JAOUEN HERVE

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L27/10 ,  H01L29/92 ,  H01L23/522

    Abstract: Production of a metal-metal capacitor within an IC is carried out by forming the two metal electrodes (40, 71) and the dielectric layer (61) on the lower insulating layer (2) bearing a metallisation level (M1) of the IC before depositing the upper insulating layer (80) for covering the metallisation level (M1). Also claimed is an IC including a metal-metal capacitor (40, 61, 71) produced as described above. Preferably, the first capacitor electrode (40) is part of the metallisation level (preferably aluminium), the second electrode (70, 71) is a thinner layer preferably of aluminium or tungsten and the dielectric layer (61) is a thin SiO2, Si3N4 or Ta2O5 layer.

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