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    73.
    发明专利
    未知

    公开(公告)号：IT1318318B1

    公开(公告)日：2003-07-28

    申请号：ITMI20001804

    申请日：2000-08-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PIERLUIGI ,  GUATINI GIOVANNI ,  PASOTTI MARCO

    IPC: G06F1/26

    Abstract: An electronic circuit for controlling voltage signals at particular critical nodes of an electronic device connected to the circuit, said circuit being inserted between a supply voltage reference and a ground voltage reference, and having at least one internal reference node connected to the critical nodes, and including at least one capacitive element inserted between the supply voltage reference and the ground voltage reference, and connected to the internal reference node through a charging device, said capacitive element being charged with the supply voltage reference to maintain, at the internal reference node, a voltage value above a predetermined threshold voltage as the supply voltage reference is cut off.

    74.
    发明专利
    未知

    公开(公告)号：IT1312471B1

    公开(公告)日：2002-04-17

    申请号：ITMI991017

    申请日：1999-05-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C11/56 ,  G11C16/34

    Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.

    75.
    发明专利
    未知

    公开(公告)号：ITMI20001804A1

    公开(公告)日：2002-02-04

    申请号：ITMI20001804

    申请日：2000-08-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PIERLUIGI ,  PASOTTI MARCO ,  GUATINI GIOVANNI

    IPC: G06F1/26

    Abstract: An electronic circuit for controlling voltage signals at particular critical nodes of an electronic device connected to the circuit, said circuit being inserted between a supply voltage reference and a ground voltage reference, and having at least one internal reference node connected to the critical nodes, and including at least one capacitive element inserted between the supply voltage reference and the ground voltage reference, and connected to the internal reference node through a charging device, said capacitive element being charged with the supply voltage reference to maintain, at the internal reference node, a voltage value above a predetermined threshold voltage as the supply voltage reference is cut off.

    76.
    发明专利
    未知

    公开(公告)号：ITMI20000832A1

    公开(公告)日：2001-10-15

    申请号：ITMI20000832

    申请日：2000-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI ,  ROCCHI ALESSANDRO ,  BISIO MARCO ,  DE SANDRE GUIDO ,  PASOTTI MARCO

    IPC: G01R31/28

    Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

    77.
    发明专利
    未知

    公开(公告)号：ITRM20010525D0

    公开(公告)日：2001-08-30

    申请号：ITRM20010525

    申请日：2001-08-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GUAITINI GIOVANNI ,  PASOTTI MARCO ,  DE SANDRE GUIDO ,  IEZZI DAVID ,  POLES MARCO ,  ROLANDI PIERLUIGI

    IPC: G11C16/08 ,  G11C16/16

    Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.

    78.
    发明专利
    未知

    公开(公告)号：DE69520673D1

    公开(公告)日：2001-05-17

    申请号：DE69520673

    申请日：1995-09-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GERNA DANILO ,  PASOTTI MARCO ,  MARCHESE STEFANO

    IPC: G11C27/00 ,  G11C27/02

    Abstract: The speed of a capacitive cell RAAM used for storing an optical image as electric charge is greatly enhanced by presampling the serial analog input signal on two rows or lines of presampling capacitors, each composed of the same number of capacitors as the number of columns of the capacitive cell RAAM and by "writing" in a parallel mode the selected row of said memory. The values stored in the capacitors of one of said two presampling rows are transferred (written) in the corresponding cells of the selected row of the memory while presampling continues on the other row of presampling capacitors.

    79.
    发明专利
    未知

    公开(公告)号：ITTO980961A1

    公开(公告)日：2000-05-15

    申请号：ITTO980961

    申请日：1998-11-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANEGALLO ROBERTO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C16/12

    Abstract: The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.

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