公开(公告)号：EP0747686B1

公开(公告)日：1999-04-14

申请号：EP96401129.0

申请日：1996-05-24

Applicant: SSI TECHNOLOGIES, INC.

Inventor： Seefeldt, James D. ,  Mattes, Michael F.

IPC: G01L9/00 ,  G01P15/08 ,  H01L29/84

CPC classification number: B81C1/00158 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0178 ,  G01L9/0042 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  Y10S438/96

公开(公告)号：KR1020030088422A

公开(公告)日：2003-11-19

申请号：KR1020037008307

申请日：2001-12-13

Applicant: 로베르트 보쉬 게엠베하

Inventor： 벤첼후베르트 ,  베버헤리베르트 ,  아르트만한스 ,  쉐퍼프랑크

IPC: B81B3/00

CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/0178

Abstract: 본 발명은 기판(1)과, 박막 영역(10a)을 포함하고 기판(1) 상부에 제공되는 단결정층(10)과, 박막 영역(10a)의 하부에 제공된 중공실(50)과, 둘러싸인 층(10)에 비해 상승된 도핑(n
+ , p
+ )을 포함하는 단결정층(10) 내에 제공된 하나 이상의 다공 영역(150, 150')을 포함하는 마이크로 기계식 구성 요소를 제공한다.

公开(公告)号：KR1020020004135A

公开(公告)日：2002-01-16

申请号：KR1020000037659

申请日：2000-07-03

Applicant: 조동일

Inventor： 조동일 ,  이상우 ,  박상준

IPC: B81C1/00

CPC classification number: B81C1/0019 ,  B81C2201/0178 ,  H01L21/764

Abstract: PURPOSE: A method for insulating a fine structure of a single crystalline silicon using a triple layer is provided to insulate a fine structure of a single crystalline silicon without an additional photo/etch process. CONSTITUTION: A thermal oxide layer is formed on a fine structure of single crystalline silicon by performing a thermal oxidation process. A conductive layer is insulated electrically with a single crystalline silicon substrate by the thermal oxide layer. A doped polysilicon layer is deposited on a surface of the thermal oxide layer by using an LPCVD(Low Pressure Chemical Vapor Deposition) method. An aluminium layer is deposited on an upper portion of a trench and a part of a sidewall of the trench by using a sputtering method or a deposition method. Each electrode is insulated by etching the deposited polysilicon layer and removing a part of the deposited polysilicon.

Abstract translation: 目的：提供使用三层绝缘单晶硅的精细结构的方法，以在没有额外的光刻/蚀刻工艺的情况下使单晶硅的精细结构绝缘。 构成：通过进行热氧化处理，在单晶硅的精细结构上形成热氧化层。 导电层通过热氧化层与单晶硅衬底电绝缘。 通过使用LPCVD（低压化学气相沉积）方法在热氧化物层的表面上沉积掺杂多晶硅层。 通过溅射法或沉积法将铝层沉积在沟槽的上部和沟槽的侧壁的一部分上。 通过蚀刻沉积的多晶硅层并去除一部分沉积的多晶硅来将每个电极绝缘。

公开(公告)号：KR1020080097243A

公开(公告)日：2008-11-04

申请号：KR1020087023570

申请日：2007-03-28

Applicant: 가부시키가이샤 고베 세이코쇼

Inventor： 히라노다까유끼 ,  가와까미노부유끼 ,  간나까마사또

IPC: H01L21/316 ,  H01L31/101

CPC classification number: G01F1/692 ,  B81B2201/0278 ,  B81B2203/0127 ,  B81C1/00666 ,  B81C2201/0169 ,  B81C2201/0178 ,  C23C16/402 ,  C23C16/56 ,  Y10T428/24488 ,  Y10T428/24612

Abstract: A membrane structure element which can be easily manufactured, has excellent insulating characteristics and a high quality is provided. A method for manufacturing such membrane structure element is also provided. The membrane structure element is provided with a membrane formed of a silicon oxide film, and a substrate for supporting the membrane in a hollow status by supporting a part of the periphery of the membrane. The method for manufacturing such membrane is provided with a film forming step of forming a heat-shrinkable silicon oxide film (13) on the surface side of a silicon substrate (2) by plasma CVD method; a heat treatment step of performing heat treatment for making the silicon oxide film (13) formed on the substrate (1) shrink with heat; and a removing step of removing a part of the substrate (2) so that a corresponding part of the silicon oxide film (13) to the membrane is supported as a membrane to the substrate (2) in the hollow status, and forming a recessed section (4).

Abstract translation: 提供了可以容易地制造的膜结构元件，具有优异的绝缘特性和高质量。 还提供了一种制造这种膜结构元件的方法。 膜结构元件设置有由氧化硅膜形成的膜，以及用于通过支撑膜的周边的一部分来将膜支撑在中空状态的基板。 该膜的制造方法具有通过等离子体CVD法在硅衬底（2）的表面侧形成热收缩性氧化硅膜（13）的成膜工序; 进行热处理的热处理步骤使得形成在基板（1）上的氧化硅膜（13）热收缩; 以及去除所述基板（2）的一部分以使得所述膜的所述氧化硅膜（13）的相应部分以中空状态作为膜被支撑到所述基板（2）的去除步骤，并且形成凹陷 第（4）节。

公开(公告)号：KR1020020050137A

公开(公告)日：2002-06-26

申请号：KR1020010080791

申请日：2001-12-18

Applicant: 미쓰비시덴키 가부시키가이샤

Inventor： 이즈오신이치 ,  오지히로시 ,  츠츠미가즈히코

IPC: C12M1/00

CPC classification number: B81C1/00111 ,  B81B2201/0214 ,  B81C2201/0114 ,  B81C2201/0178 ,  G01N27/44791

Abstract: PURPOSE: To provide a method of manufacturing a structure having, on a silicon substrate, columnar structures which are uniform in shape and have an enough heat resistance and mechanical strength, and also to provide a DNA segregating device manufactured by the method. CONSTITUTION: The structure has, on the silicon substrate, columns whose principal planes are coated with a thermal oxide film. The columns are formed of only a thermal oxide film or of a thermal oxide film and silicon. The thermal oxide film formed on the principal planes of the columns is connected to a thermal oxide film formed on the surface of the substrate or inside the substrate.

Abstract translation: 目的：提供一种制造在硅衬底上具有均匀形状且具有足够的耐热性和机械强度的柱状结构的结构的方法，并且还提供了通过该方法制造的DNA分离装置。 构成：该结构在硅衬底上具有其主平面涂覆有热氧化膜的色谱柱。 柱仅由热氧化膜或热氧化膜和硅形成。 在柱的主平面上形成的热氧化膜与形成在基板的表面或基板内部的热氧化膜连接。

公开(公告)号：US20240165663A1

公开(公告)日：2024-05-23

申请号：US18347113

申请日：2023-07-05

Applicant: The Board of Trustees of the Leland Stanford Junior University

Inventor： Bo Ma ,  Kamyar Firouzi ,  Butrus T. Khuri-Yakub ,  Jose Joseph

IPC: B06B1/02 ,  B06B1/06 ,  B81B3/00 ,  B81C1/00 ,  G01N29/06 ,  G01N29/22 ,  G01N29/24

CPC classification number: B06B1/0215 ,  B06B1/0292 ,  B06B1/0651 ,  B06B1/0662 ,  B81B3/0021 ,  B81C1/00166 ,  G01N29/0654 ,  G01N29/2406 ,  B06B2201/55 ,  B81B2201/0271 ,  B81B2203/04 ,  B81C2201/0157 ,  B81C2201/0178 ,  G01N29/22

Abstract: Aspects of this disclosure relate to driving a capacitive micromachined ultrasonic transducer (CMUT) with a pulse train of unipolar pulses. The CMUT may be electrically excited with a pulse train of unipolar pulses such that the CMUT operates in a continuous wave mode. In some embodiments, the CMUT may have a contoured electrode.

公开(公告)号：US20230312334A1

公开(公告)日：2023-10-05

申请号：US18124788

申请日：2023-03-22

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Siarhei Dmitrievich Barsukou

IPC: B81B3/00 ,  H10N30/30 ,  B81C1/00 ,  H10N30/87 ,  H04R17/02

CPC classification number: B81B3/0021 ,  H10N30/30 ,  B81C1/0015 ,  H10N30/872 ,  H04R17/02 ,  B81B2201/0257 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81B2203/0307 ,  B81B2203/0315 ,  B81B2203/04 ,  H04R2201/003 ,  B81C2201/0178 ,  B81C2201/013

Abstract: A piezoelectric microelectromechanical systems microphone is provided comprising a sensor, an anchor region at which the sensor is supported by a substrate, a first region of the sensor adjacent to the anchor region, the first region having at least one piezoelectric layer and at least one electrode, and a second region of the sensor, the second region being adjacent to the first region, having at least one piezoelectric layer and at least one electrode, and having a thickness less than the thickness of the first region. A method for manufacturing a piezoelectric microelectromechanical systems microphone is also provided.

公开(公告)号：US20180148328A1

公开(公告)日：2018-05-31

申请号：US15825818

申请日：2017-11-29

Applicant: Commissariat a l'energie atomique et aux energies alternatives

Inventor： Vincent AGACHE ,  Francois BALERAS

IPC: B81C1/00

CPC classification number: B81C1/00476 ,  B81B3/0021 ,  B81B2201/0214 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81C1/00944 ,  B81C1/00952 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0178 ,  B81C2201/0181 ,  B81C2201/019 ,  B81C2201/053

Abstract: The invention is a process for producing an electromechanical device including a movable portion that is able to deform with respect to a fixed portion. The process implements steps based on fabrication microtechnologies, applied to a substrate including an upper layer, an intermediate layer and a lower layer. These steps are: a) forming first apertures in the upper layer; b) forming an empty cavity in the intermediate layer, which step is referred to as a pre-release step because a central portion of the upper layer lying between the first apertures is pre-released; c) applying what is called a blocking layer to the upper layer, this layer covering the first apertures, the blocking layer and the central portion together forming a suspended microstructure above the empty cavity; d) producing a boundary trench in the suspended microstructure, so as to form, in this microstructure, a movable portion and a fixed portion, the movable portion forming a movable member of the electromechanical device.

公开(公告)号：US08992784B2

公开(公告)日：2015-03-31

申请号：US13386049

申请日：2010-07-20

Applicant: Nakis Karapatis

Inventor： Nakis Karapatis

IPC: B81C1/00

CPC classification number: B81C1/00682 ,  B81B2201/035 ,  B81C1/00674 ,  B81C2201/0178 ,  Y10T29/49986

Abstract: A method of fabricating a reinforced silicon micromechanical part includes: micro-machining the part, or a batch of parts in a silicon wafer; forming a silicon dioxide layer over the entire surface of the part, in one or plural operations, so as to obtain a thickness of silicon dioxide that is at least five times greater than the thickness of native silicon dioxide; and removing the silicon dioxide layer by etching.

Abstract translation: 制造增强硅微机械部件的方法包括：在硅晶片中对所述部件或一批部件进行微加工; 在一个或多个操作中在整个表面上形成二氧化硅层，以获得比天然二氧化硅的厚度大至少五倍的二氧化硅的厚度; 并通过蚀刻去除二氧化硅层。

公开(公告)号：US08828772B2

公开(公告)日：2014-09-09

申请号：US13412257

申请日：2012-03-05

Applicant: Te-Hao Lee

Inventor： Te-Hao Lee

IPC: H01L21/316

CPC classification number: B81C1/00619 ,  B81C2201/0122 ,  B81C2201/0178

Abstract: An HF vapor etch etches high aspect ratio openings to form MEMS devices and other tightly-packed semiconductor devices with 0.2 um air gaps between structures. The HF vapor etch etches oxide plugs and gaps with void portions and oxide liner portions and further etches oxide layers that are buried beneath silicon and other structures and is ideally suited to release cantilevers and other MEMS devices. The HF vapor etches at room temperature and atmospheric pressure in one embodiment. A process sequence is provided that forms MEMS devices including cantilevers and lateral, in-plane electrodes that are stationary and vibration resistant.

Abstract translation: HF蒸汽蚀刻蚀刻高纵横比开口以形成MEMS器件和其他紧密堆积的半导体器件，其中在结构之间具有0.2um的气隙。 HF蒸汽蚀刻蚀刻具有空隙部分和氧化物衬垫部分的氧化物塞和间隙，并进一步蚀刻氧化物层，其被埋在硅和其它结构之下，并且理想地适合于释放悬臂和其它MEMS器件。 在一个实施方案中，HF蒸气在室温和大气压下蚀刻。 提供了一种形成MEMS器件的工艺顺序，其包括静止和抗振动的悬臂和侧向平面内的电极。