公开(公告)号：US20030168512A1

公开(公告)日：2003-09-11

申请号：US10339281

申请日：2003-01-09

Applicant: Hand Held Products, Inc.

Inventor： Andrew Longacre JR. ,  William H. Havens ,  Robert J. Hennick ,  Vivian L. Hunter ,  John Izzo ,  Michael D. Robinson

IPC: G06K007/10 ,  G06K007/14

CPC classification number: G06K7/10861 ,  G06K7/10584 ,  G06K7/10722 ,  G06K7/10801 ,  G06K7/14 ,  H05K1/18 ,  H05K3/244 ,  H05K2201/09072 ,  H05K2201/09463 ,  H05K2201/0949 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2201/10121

Abstract: A one-dimensional optical reader which senses a position of a decodable symbol representation in captured image data and which utilizes the sensed position information to determine whether to launch a decoding algorithm to decode the symbol representation.

Abstract translation: 感测捕获的图像数据中的可解码符号表示的位置并且利用所感测的位置信息来确定是否启动解码算法以解码符号表示的一维光学读取器。

公开(公告)号：US5962922A

公开(公告)日：1999-10-05

申请号：US40472

申请日：1998-03-18

Applicant: Bily Wang

Inventor： Bily Wang

IPC: H01L23/13 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H05K3/3436 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/116 ,  H05K2201/09463 ,  H05K2201/09472 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2201/10666 ,  H05K2203/1178 ,  Y02P70/613

Abstract: A flat package for integrated circuit chip has a substrate with plated through holes. The top flange of a plated through hole is interconnected to a terminal of the IC chip. The bottom flange of the through hole has a cavity recessed into the substrates. A solder is placed between a circuit contact on a mother board and the bottom flange. Upon heating, the solder rises to fill the cavity, to make connection between the terminal on the IC chip and the contact on the mother board.

Abstract translation: 用于集成电路芯片的扁平封装具有带有电镀通孔的基板。 电镀通孔的顶部凸缘与IC芯片的端子互连。 通孔的底部凸缘具有凹入基板的腔体。 焊料放置在母板上的电路触点和底部法兰之间。 在加热时，焊料上升以填充空腔，以使IC芯片上的端子和母板上的触点之间的连接。

公开(公告)号：US09480141B1

公开(公告)日：2016-10-25

申请号：US14032908

申请日：2013-09-20

Applicant: Junis Hamadeh

Inventor： Junis Hamadeh

IPC: H05K1/02 ,  H01R12/00

CPC classification number: H01R12/00 ,  H05K1/0206 ,  H05K1/021 ,  H05K1/113 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09463 ,  H05K2201/0959 ,  H05K2201/10106 ,  H05K2201/10401 ,  H05K2201/10416

Abstract: A heat sinking rapid assembly semiconductor package comprising an electrically segmented conductive assembly post. The post is fabricated comprising at least two independent electrically conductive segments separated by an electrically isolating element. An electrical component, such as a semiconductor device, is assembled to an upper portion of the conductive post, wherein each contact of the component is in electrical communication with a respective conductive segment. The post can be mechanically pressed, threaded, or mechanically coupled using any other reasonable mechanical interface into a segmented via or plated-through hole of a printed circuit board (PCB). The electrical segments would be in electrical communication with conductive portions of the segmented via to form a complete electrical circuit between the PCB and the electrical component. A thermally conductive element can be integrated into the post to conduct heat away from the semiconductor device to improve performance and reduce failures related to thermal stress.

Abstract translation: 一种散热快速组装半导体封装，包括电分段的导电组件柱。 该柱被制造成包括由电隔离元件隔开的至少两个独立的导电段。 诸如半导体器件的电气部件被组装到导电柱的上部，其中部件的每个触点与相应的导电部分电连通。 可以使用任何其他合理的机械接口将柱机械地压制，螺纹化或机械耦合到印刷电路板（PCB）的分段通孔或电镀通孔中。 电段将与分段通孔的导电部分电连通，以在PCB和电气部件之间形成完整的电路。 导热元件可以集成到柱中以将热量从半导体器件导出，以提高性能并减少与热应力相关的故障。

公开(公告)号：US08399774B2

公开(公告)日：2013-03-19

申请号：US13303769

申请日：2011-11-23

Applicant: Yoichi Hitomi ,  Hiroaki Miyazawa ,  Shinji Kumon ,  Terutoshi Momose

Inventor： Yoichi Hitomi ,  Hiroaki Miyazawa ,  Shinji Kumon ,  Terutoshi Momose

IPC: H05K1/00 ,  H05K1/02

CPC classification number: G06F1/182 ,  G11B5/40 ,  G11B5/484 ,  G11B5/4853 ,  H05K1/0215 ,  H05K1/056 ,  H05K1/116 ,  H05K3/44 ,  H05K2201/09463 ,  H05K2201/09554

Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the insulating layer. A grounding-terminal-forming material is placed in the opening for grounding terminal to form a grounding terminal that connects the metallic substrate and the grounding conductor. The grounding conductor does not surround a portion of the circumference of the opening for grounding terminal.

Abstract translation: 悬浮基板包括金属基板，形成在金属基板上的绝缘层，具有用于接地端子的开口和形成在绝缘层上的接地导体。 接地端子形成材料放置在接地端子的开口中，形成连接金属基板和接地导体的接地端子。 接地导体不包围用于接地端子的开口的圆周的一部分。

公开(公告)号：US08143976B2

公开(公告)日：2012-03-27

申请号：US12607027

申请日：2009-10-27

Applicant: Christopher P. Wyland

Inventor： Christopher P. Wyland

IPC: H01P7/08 ,  H03H7/38

CPC classification number: H01L23/66 ,  H01L23/64 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09463 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

Abstract: Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via.

Abstract translation: 差分信号的通孔通常比与其相连的信号线阻抗更低。 导致阻抗失配的噪声和反射信号可能要求电路以远低于所需的频率运行。 本发明的一个或多个实施例避免了电路中的阻抗不匹配，并且通过向通孔的每个端部添加裂环谐振器（SSR）提供具有较高阻抗的通孔来实现本领域的进步。

公开(公告)号：US20110141707A1

公开(公告)日：2011-06-16

申请号：US13032546

申请日：2011-02-22

Applicant: Kenji Hasegawa ,  Tsuyoshi Kozai ,  Terunari Kanou

Inventor： Kenji Hasegawa ,  Tsuyoshi Kozai ,  Terunari Kanou

IPC: H05K5/02

CPC classification number: H05K1/02 ,  H05K1/0215 ,  H05K1/116 ,  H05K3/325 ,  H05K5/0247 ,  H05K7/142 ,  H05K9/0064 ,  H05K2201/09463 ,  H05K2201/10409

Abstract: According to an aspect of the present invention, there is provided a printed wiring board including: a substrate including an edge and a fixing hole located adjacent to the edge, the fixing hole configured to receive a bolt; and a land formed in a vicinity of the fixing hole and extending in at least a first direction and a second direction, the first direction being a direction from the fixing hole toward a center of the substrate, the second direction being direction along the edge.

Abstract translation: 根据本发明的一个方面，提供了一种印刷线路板，包括：基板，其包括边缘和邻近边缘定位的固定孔，所述固定孔构造成接收螺栓; 以及形成在所述固定孔附近并且沿至少第一方向和第二方向延伸的台阶，所述第一方向是从所述固定孔朝向所述基板的中心的方向，所述第二方向是沿着所述边缘的方向。

公开(公告)号：US20110095851A1

公开(公告)日：2011-04-28

申请号：US12607027

申请日：2009-10-27

Applicant: Christopher P. Wyland

Inventor： Christopher P. Wyland

IPC: H01P7/08

CPC classification number: H01L23/66 ,  H01L23/64 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09463 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

Abstract: Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via.

Abstract translation: 差分信号的通孔通常比与其相连的信号线阻抗更低。 导致阻抗失配的噪声和反射信号可能要求电路以远低于所需的频率运行。 本发明的一个或多个实施例避免了电路中的阻抗不匹配，并且通过向通孔的每个端部添加裂环谐振器（SSR）提供具有较高阻抗的通孔来实现本领域的进步。

公开(公告)号：US07791425B2

公开(公告)日：2010-09-07

申请号：US11975753

申请日：2007-10-22

Applicant: Takeshi Uchida ,  Manabu Ito ,  Tomotaka Kuroda

Inventor： Takeshi Uchida ,  Manabu Ito ,  Tomotaka Kuroda

IPC: H03B1/00 ,  H03B5/32

CPC classification number: H01R43/0256 ,  H01R12/52 ,  H05K1/141 ,  H05K3/3447 ,  H05K3/368 ,  H05K2201/09036 ,  H05K2201/09463 ,  H05K2201/10303 ,  H05K2201/1084 ,  H05K2201/10871 ,  H05K2203/1178 ,  Y10T428/24612

Abstract: The present invention relates to a two-level mounting board in which a second substrate is supported horizontally by a metal pin above a first substrate having a mounting electrode on an outer base surface, the free, lower end of the metal pin is inserted in a hole provided in the surface of the first substrate, and the metal pin is affixed by solder to an annular electrode land provided on the surface of the first substrate to form an outer periphery of the hole, wherein part of the ring of the annular electrode land is cut away to open the same. This provides a two-level mounting board in which metal pins can be connected reliably to the first substrate to support the second substrate horizontally, and a crystal oscillator using the same.

Abstract translation: 本发明涉及一种二级安装板，其中第二基板由位于外基座表面上的具有安装电极的第一基板上的金属销水平支撑，金属销的自由下端插入 并且所述金属销通过焊料固定到设置在所述第一基板的表面上的环形电极焊盘，以形成所述孔的外周，其中所述环形电极的环的一部分 被切开打开一样。 这提供了两级安装板，其中金属引脚可以可靠地连接到第一基板以水平地支撑第二基板，以及使用其的晶体振荡器。

公开(公告)号：US20100061067A1

公开(公告)日：2010-03-11

申请号：US12470370

申请日：2009-05-21

Applicant: Kenji Hasegawa ,  Tsuyoshi Kozai ,  Terunari Kanou

Inventor： Kenji Hasegawa ,  Tsuyoshi Kozai ,  Terunari Kanou

IPC: H05K5/00 ,  H05K1/00

CPC classification number: H05K1/02 ,  H05K1/0215 ,  H05K1/116 ,  H05K3/325 ,  H05K5/0247 ,  H05K7/142 ,  H05K9/0064 ,  H05K2201/09463 ,  H05K2201/10409

Abstract: According to an aspect of the present invention, there is provided a printed wiring board including: a substrate including an edge and a fixing hole located adjacent to the edge, the fixing hole configured to receive a bolt; and a land formed in a vicinity of the fixing hole and extending in at least a first direction and a second direction, the first direction being a direction from the fixing hole toward a center of the substrate, the second direction being direction along the edge.

Abstract translation: 根据本发明的一个方面，提供了一种印刷线路板，包括：基板，其包括边缘和邻近边缘定位的固定孔，所述固定孔构造成接收螺栓; 以及形成在所述固定孔附近并且沿至少第一方向和第二方向延伸的台阶，所述第一方向是从所述固定孔朝向所述基板的中心的方向，所述第二方向是沿着所述边缘的方向。

公开(公告)号：US07508069B2

公开(公告)日：2009-03-24

申请号：US11436946

申请日：2006-05-18

Applicant: James Douglas Wehrly, Jr. ,  Ron Orris ,  Leland Szewerenko ,  Tim Roy ,  Julian Partridge ,  David L. Roper

Inventor： James Douglas Wehrly, Jr. ,  Ron Orris ,  Leland Szewerenko ,  Tim Roy ,  Julian Partridge ,  David L. Roper

IPC: H01L23/34

CPC classification number: H01L25/18 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/49175 ,  H01L2924/15311 ,  H05K1/147 ,  H05K1/189 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3436 ,  H05K3/3447 ,  H05K2201/055 ,  H05K2201/091 ,  H05K2201/09463 ,  H05K2201/10515 ,  H05K2201/10689

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

Abstract translation: 本发明提供一种用于使用柔性电路组合引线封装IC和半导体管芯以减少组合的覆盖区的系统和方法。 引线IC封装沿柔性电路的正面设置。 在优选实施例中，引线IC封装的引线被配置为允许引线IC封装的主体的下表面通过粘合剂直接或间接地接触柔性电路的表面。 半导体管芯连接到柔性电路的反面。 在一个实施例中，半导体管芯设置在柔性反面的另一侧，而在替代实施例中，将半导体管芯设置在柔性电路中的窗口中，以直接或间接地安置在引线IC封装体上。 模块触点以各种配置提供。 在优选实施例中，引线IC封装是闪存，半导体管芯是控制器。