公开(公告)号：EP4398311A1

公开(公告)日：2024-07-10

申请号：EP23190757.7

申请日：2023-08-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Richter, Ralf ,  Dünkel, Stefan ,  Sessi, Violetta

IPC: H01L29/423 ,  H10B41/30 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/42328 ,  H01L29/7885 ,  H01L29/40114

Abstract: The disclosure provides a structure (100) with a buried doped region (112) for coupling a source line contact (114) to the gate structure (110) of a memory cell (104). A structure according to the disclosure includes a memory cell having a gate structure extending in a first lateral direction (X) over a substrate (102). A buried doped region is within the substrate and extends in a second lateral direction (Y) from below the gate structure to a portion of the substrate laterally distal to the gate structure. A source line contact is on the portion of the substrate laterally distal to the gate structure. The buried doped region couples the source line contact to the gate structure of the memory cell through a lower surface of the gate structure.

公开(公告)号：EP4398030A1

公开(公告)日：2024-07-10

申请号：EP23205376.9

申请日：2023-10-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： JAIN, Vibhor ,  BIAN, Yusheng ,  PANDEY, Shesh Mani ,  ABOKETAF, Abdelsalam ,  SRIVASTAVA, Ravi Prakash

IPC: G02F1/225

CPC classification number: G02F1/225 ,  G02F2203/2120130101

Abstract: Structures including an optical phase shifter and methods of forming a structure including an optical phase shifter. The structure comprises an optical phase shifter including a waveguide core having a first branch and a second branch laterally spaced from the first branch. The structure further comprises a thermoelectric device including a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit. The first plurality of pillars and the second plurality of pillars disposed adjacent to the first branch of the waveguide core, the first plurality of pillars comprises an n-type semiconductor material, and the second plurality of pillars comprises a p-type semiconductor material.

公开(公告)号：EP4387410A1

公开(公告)日：2024-06-19

申请号：EP23197413.0

申请日：2023-09-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gopinath, Venkatesh P. ,  Jain, Navneet ,  Ren, Hongru ,  Derrickson, Alexander ,  Peng, Jianwei ,  Paul, Bipul C.

IPC: H10B63/00 ,  H10N70/20 ,  H01L27/12

CPC classification number: H10N70/20 ,  H01L27/1259 ,  H10B63/30 ,  H10B63/80 ,  H10N70/826 ,  H10N70/8833 ,  H01L27/1222 ,  G11C2213/7920130101 ,  G11C2213/7420130101 ,  G11C13/003 ,  G11C11/1659

Abstract: Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.

公开(公告)号：EP4386843A1

公开(公告)日：2024-06-19

申请号：EP23198237.2

申请日：2023-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Kantarovsky, Johnatan Avraham ,  Krishnasamy, Rajendran

IPC: H01L27/02

CPC classification number: H01L29/1066 ,  H01L29/404 ,  H01L29/2003 ,  H01L29/7786

Abstract: An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

公开(公告)号：EP4386830A1

公开(公告)日：2024-06-19

申请号：EP23201726.9

申请日：2023-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pandey, Shesh Mani ,  Levy, Mark D. ,  Tan, Chung Foong

IPC: H01L23/34 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/345

Abstract: A fuse structure includes a fuse body including a polysilicon, and a metal heater over the fuse body. The fuse structure also includes a heating spreading structure thermally coupled to the metal heater and extending horizontally adjacent to at least one side of the fuse body. The metal heater can be a portion of a metal wire or a resistor including a resistive metal. The heat spreading structure may include a plurality of metal contacts.

公开(公告)号：EP4383357A1

公开(公告)日：2024-06-12

申请号：EP23199267.8

申请日：2023-09-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： DERRICKSON, Alexander ,  RAGHUNATHAN, Uppili S. ,  JAIN, Vibhor ,  BIAN, Yusheng ,  HOLT, Judson R.

IPC: H01L31/11 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/0232 ,  H01L31/0224

CPC classification number: H01L31/1105 ,  H01L31/028 ,  H01L31/02327 ,  H01L31/035281 ,  H01L31/022408

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to lateral phototransistors and methods of manufacture. The structure includes a lateral bipolar transistor (12); and a T-shaped photosensitive structure (20) vertically above an intrinsic base (12d) of the lateral bipolar transistor.

公开(公告)号：EP4376094A2

公开(公告)日：2024-05-29

申请号：EP23196323.2

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Borisov, Kiril Biserov ,  Darwish, Mohammed Ahmed Fouad Ibrahim ,  Weisbuch, Francois C. ,  Elshafie, Shady Ahmed Abdelwahed Ahmed ,  Pritchard, David Charles ,  Ramadout, Benoit Francois Claude

IPC: H01L29/78 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L29/0692 ,  H01L29/78

Abstract: Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A first gate structure extends over the first edge, and entirely covers the first edge and the first corner segment of the semiconductor region.

公开(公告)号：EP4375717A1

公开(公告)日：2024-05-29

申请号：EP23201857.2

申请日：2023-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pandey, Shesh Mani ,  Bian, Yusheng ,  Srivastava, Ravi Prakash

IPC: G02B6/12 ,  G02B6/132 ,  G02B6/136

CPC classification number: G02B6/12002 ,  G02B6/136 ,  G02B6/12004 ,  G02B6/132 ,  G02B2006/1206120130101

Abstract: Structures and methods implement an enlarged multilayer nitride waveguide. The structure may include an inter-level dielectric (ILD) layer over a substrate. A first enlarged multilayer nitride waveguide is positioned in the ILD layer in a region of the substrate. A second multilayer nitride waveguide may also be provided in the ILD layer. A lower cladding layer defines a lower surface of the nitride waveguide(s). The lower cladding layer has a lower refractive index than the nitride waveguide(s). Additional lower refractive index cladding layers can be provided on the upper surface and/or sidewalls of the nitride waveguide(s). The enlarged nitride waveguide may be implemented with other conventional silicon and nitride waveguides.

公开(公告)号：EP4373237A1

公开(公告)日：2024-05-22

申请号：EP23198101.0

申请日：2023-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： DERRICKSON, Alexander ,  GOPINATH, Venkatesh ,  PEKARIK, John J. ,  YU, Hong ,  JAIN, Vibhor ,  PRITCHARD, David

IPC: H10B63/00 ,  H01L27/102 ,  H10B61/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/32 ,  H10B61/20 ,  H10B63/80 ,  H10N70/20 ,  H10N70/826 ,  H10N70/883 ,  H10N70/8833 ,  H01L27/1022

Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate (32), and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor (12) including a first collector in the substrate (34), a first emitter (40), and a first base layer (20). The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor (14) including a second collector (34) in the substrate, a second emitter (42), and a second base layer (22). The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

公开(公告)号：EP4373236A1

公开(公告)日：2024-05-22

申请号：EP23197829.7

申请日：2023-09-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： PEKARIK, John J. ,  YU, Hong ,  JAIN, Vibhor ,  DERRICKSON, Alexander ,  GOPINATH, Venkatesh

IPC: H10B63/00 ,  H01L27/102 ,  H10B61/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/32 ,  H10N70/826 ,  H10B61/20 ,  H10B63/80 ,  H10N70/20 ,  H10N70/883 ,  H10N70/8833 ,  H01L27/1022

Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure (10) comprises a substrate (32) having a top surface, a trench isolation region (24) in the substrate, and a base layer (20) on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor (12) includes a first collector (34) in the substrate and a first emitter (40) on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor (16) includes a second collector (36) in the substrate and a second emitter (44) on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.