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公开(公告)号：KR101531870B1
公开(公告)日：2015-06-29
申请号：KR1020130165606
申请日：2013-12-27
Applicant: (재)한국나노기술원
IPC: H01L21/20
CPC classification number: H01L21/76807 , H01L21/32055 , H01L21/7684 , H01L21/76877
Abstract: 본발명은실리콘기판상에화합물반도체소자를제조하는방법에있어서, 실리콘기판을준비하는제1단계, 상기실리콘기판상에산화막을증착시키는제2단계, 상기산화막을패터닝하여, 상기실리콘기판의일부영역을노출시키면서, 상기실리콘기판상에는계단형트렌치를형성하는제3단계, 상기계단형트렌치형성후, 노출된상기실리콘기판영역과상기계단형트렌치상측에화합물반도체층을성장시키는제4단계를포함하여이루어지는것을특징으로하는계단형트렌치를이용하여실리콘기판상에대면적화합물반도체소자를형성하는방법을기술적요지로한다. 이에의해실리콘기판상에계단형트렌치를형성하여, 실리콘과화합물반도체간의계면에서발생하는관통전위를트랩시켜결함이없는(defect free) 대면적의화합물반도체소자를제공할수 있는이점이있다.
Abstract translation: 本发明涉及一种在硅衬底上制造化合物半导体器件的方法，更具体地说，涉及通过使用步骤沟槽在硅衬底上制造具有大面积的化合物半导体器件的方法，包括：制备第 硅基板; 在硅衬底上沉积氧化膜的第二步骤; 图案化氧化膜的第三步骤，暴露硅衬底的一些区域，以及在硅衬底上形成步骤沟槽; 以及形成所述台阶沟槽的第四步骤，以及在所述暴露的硅衬底区域和所述台阶沟槽的上侧上方生长化合物半导体层。 因此，在硅基板上形成台阶沟槽，从而通过捕获从硅与化合物半导体之间的界面产生的穿透电位，提供具有大面积的无缺陷化合物半导体器件。
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Patent Agency Ranking
公开(公告)号：KR1020150047828A
公开(公告)日：2015-05-06
申请号：KR1020130127788
申请日：2013-10-25
Applicant: (재)한국나노기술원
CPC classification number: H04N5/332 , H04N5/2251 , H04N5/232
Abstract: 본발명은변조적외선컬러영상획득시스템으로서, 둘이상의변조적외선파장을피사체에조사하는적외선조사장치; 적외선조사장치에의해조사되고피사체에의해반사된둘 이상의변조적외선파장을감지하고, 둘이상의변조적외선파장을변환및 조합하여컬러영상을획득하는컬러영상획득장치; 및컬러영상획득장치와미리결정된시간에보정및 동기화되고, 적외선조사장치의적외선조사시간을파장별로조정하는동기화장치를포함한다.
Abstract translation: 本发明涉及一种使用调制的红外线获得彩色图像的系统，该系统包括：向被摄体照射至少两个调制的红外波长的红外辐射装置; 检测由所述红外线照射装置照射并被所述被检体反射的经调制的红外波长的彩色图像获取装置，并且通过转换和组合调制的红外波长获得彩色图像; 以及在预定时间与彩色图像获取装置校正和同步的同步装置，并且每波长调整红外线照射装置的红外线照射时间。
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公开(公告)号：KR101450521B1
公开(公告)日：2014-10-16
申请号：KR1020130096406
申请日：2013-08-14
Applicant: (재)한국나노기술원
IPC: H01L21/3065 , H01L21/027
CPC classification number: H01L21/3065 , H01L21/0273 , H01L21/76
Abstract: The present invention relates to a method for manufacturing a semiconductor device having a silicone trench. The method measures the semiconductor device having the silicone trench using an evaporation device including a vacuum chamber. The technical point of the present invention relates to the method for manufacturing the semiconductor device having the silicone trench, comprising: a first step of preparing a silicone substrate; a second step of evaporating an oxide film on the silicone substrate; a third step of forming a trench on the silicon substrate after patterning the oxide film; a fourth step of forming a trench etching area so that an area (111) of the silicone is shown through a heat transmission process after the formation of the trench; and a fifth step of evaporating a compound semiconductor after the formation of the trench etching area. Therefore, a natural oxide film of the surface of the silicon trench can be eliminated completely by forming a ′V′-shaped or ′U′-shaped trench etching area. A penetration potential (threading dislocation) produced on the silicone and III-V compound semiconductor interface reduces the height which is fixated on the sidewall, and an indefective III-V compound semiconductor of a wide area can be grown. Therefore, a semiconductor device of high quality can be provided.
Abstract translation: 本发明涉及一种具有硅氧烷沟槽的半导体器件的制造方法。 该方法使用包括真空室的蒸发装置测量具有硅氧烷沟槽的半导体器件。 本发明的技术要点涉及制造具有硅氧烷沟槽的半导体器件的方法，包括：制备硅树脂衬底的第一步骤; 在硅树脂基板上蒸发氧化膜的第二步骤; 在图案化氧化膜之后在硅衬底上形成沟槽的第三步骤; 形成沟槽蚀刻区域的第四步骤，使得在形成沟槽之后通过热传递过程示出硅树脂的区域（111）; 以及在形成沟槽蚀刻区域之后蒸发化合物半导体的第五步骤。 因此，通过形成“V”形或“U”形沟槽蚀刻区域，可以完全消除硅沟槽表面的自然氧化膜。 在硅酮和III-V化合物半导体界面上产生的穿透电位（穿透位错）降低了固定在侧壁上的高度，并且可以生长广泛区域的不完全的III-V化合物半导体。 因此，可以提供高质量的半导体器件。
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公开(公告)号：KR1020130133986A
公开(公告)日：2013-12-10
申请号：KR1020120057164
申请日：2012-05-30
Applicant: (재)한국나노기술원
IPC: H01L31/042 , H01L31/06 , H01L31/18
CPC classification number: Y02E10/50 , Y02P70/521 , H01L31/042 , H01L31/06 , H01L31/18
Abstract: The invention relates to a horizontal electrode structure solar cell and manufacturing method thereof which produces the most optimized horizontal electrode structured solar cell, avoid the influence by structural deformity where the lattice misfits the dislocation of the growth regulator, and substrate is generated. The horizontal electrode structure solar cell of the present invention has an effect to increase the efficiency because the reduction does not occur since the carrier is not transmitted in the misfit dislocation layer, and the efficiency is improved by the influence of the deformity of the solar cell of which a thin film is included. The invention also comprises a wide band gap layer formed on the upper part of the thin film and the ohmic layer, the first electrode formed at the upper part of the wide band gap layer into a predetermined thickness and the device layer, and the second electrode formed in the upper part of the device of the ohmic layer. At the same time, the lattice mismatch substrate including the substrate formed on the substrate, and the lattice of the misfit dislocation of the lattice constants are included in the present invention. [Reference numerals] (130) Misfit dislocation layer;(150) Ohmic layer;(160) Device layer;(170,180) Electrode
Abstract translation: 本发明涉及一种水平电极结构太阳能电池及其制造方法，其制造最优化的水平电极结构太阳能电池，避免了晶格不适于生长调节器位错的结构变形的影响，产生了基板。 本发明的水平电极结构太阳能电池具有提高效率的效果，因为不会在不匹配位错层中传输载体而不发生还原，并且通过太阳能电池的畸变的影响来提高效率 其中包括薄膜。 本发明还包括形成在薄膜的上部和欧姆层上的宽带隙层，形成在宽带隙层的上部的第一电极和装置层，以及第二电极 形成在欧姆层的器件的上部。 同时，包括形成在基板上的基板的晶格失配基板和晶格常数的失配位错的晶格包括在本发明中。 （130）不匹配位错层;（150）欧姆层;（160）器件层;（170,180）电极
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公开(公告)号：KR101193809B1
公开(公告)日：2012-10-23
申请号：KR1020110092872
申请日：2011-09-15
Applicant: (재)한국나노기술원
Abstract: PURPOSE: A chemical semiconductor solar cell and a manufacturing method thereof are provided to prevent a galvanic effect by wet-etching a cap layer using a photoresist film as a mask. CONSTITUTION: A window layer(230) is formed on a photoelectric conversion cell and is composed of a compound semiconductor. A cap layer(240) is wet-etched on the window layer using a photoresist film as a mask. A grid metal pattern(250) is formed on the upper side of the cap layer. An antireflection layer(260) is formed in an area exposing the surface of the window layer.
Abstract translation: 目的：提供一种化学半导体太阳能电池及其制造方法，以通过使用光致抗蚀剂膜作为掩模将盖层湿法蚀刻来防止电偶效应。 构成：窗口层（230）形成在光电转换单元上，由化合物半导体构成。 使用光致抗蚀剂膜作为掩模，在窗口层上湿蚀刻覆盖层（240）。 栅格金属图案（250）形成在盖层的上侧。 在暴露窗口层的表面的区域中形成防反射层（260）。
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公开(公告)号：KR101161264B1
公开(公告)日：2012-07-02
申请号：KR1020100124812
申请日：2010-12-08
Applicant: (재)한국나노기술원
Abstract: 본 발명에 따른 반도체 소자 제조 방법에서는 기판의 한쪽 면에 제1 소자층을 형성한 다음, 상기 기판을 뒤집어 상기 기판의 다른쪽 면에 제2 소자층을 형성한다. 상기 제1 소자층에 제1 캐리어 기판을 접합하고 상기 제2 소자층에 제2 캐리어 기판을 접합한 후 상기 기판과 상기 제1 소자층 사이 및 상기 기판과 제2 소자층 사이를 분리하거나, 상기 기판과 상기 제1 소자층 사이 및 상기 기판과 제2 소자층 사이를 분리한 후 상기 제1 소자층에 제1 캐리어 기판을 접합하고 상기 제2 소자층에 제2 캐리어 기판을 접합한다. 본 발명에 따르면, 기판의 양쪽 면을 이용하고 기판을 재사용함에 따라 기판의 소모, 재료의 소모를 최소화한다. 그리고, 기판을 중심으로 동일한 방향의 힘(compressive or tensile)이 가해짐으로써 기판과 박막의 열팽창 계수의 차이로 인한 휨 현상이 억제된다.
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