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公开(公告)号：KR1020160004553A
公开(公告)日：2016-01-13
申请号：KR1020140082982
申请日：2014-07-03
Applicant: 삼성전기주식회사
Abstract: 본발명은인쇄회로기판및 그제조방법을제공한다. 구체적으로는, 본발명의일 실시예에따른인쇄회로기판은절연층, 상기절연층상에형성된회로패턴및 더미패턴을포함하며, 상기더미패턴은서로다른제1 금속및 제2 금속을포함함으로써, 휨발생을억제하거나제어할수 있고, 저항이높은상기더미패턴을이용하여상기인쇄회로기판의임피던스를조정할수 있으며, 그라운드의역할을수행할수가있다. 또한, 상기더미패턴은절연재대비열전도성이높기때문에상기인쇄회로기판의방열성을향상시킬수 있다.
Abstract translation: 提供一种印刷电路板及其制造方法。 更具体地，根据本发明的实施例，印刷电路板包括绝缘层，以及形成在绝缘层上的电路图案和虚设图案。 伪图案包括彼此不同的第一金属和第二金属，因此可以抑制或控制翘曲，通过使用具有高电阻的虚拟图案来调整印刷电路板的阻抗，并且用作接地。 此外，由于虚设图案与绝缘材料相比具有高导热性，因此可以提高印刷电路板的散热性能。
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公开(公告)号：KR101497268B1
公开(公告)日：2015-02-27
申请号：KR1020140034156
申请日：2014-03-24
Applicant: 삼성전기주식회사
IPC: H05K3/46
Abstract: 본 발명은 회로 기판에 관한 것으로, 캐비티 또는 리세스부가 형성된 무기물 절연층; 상기 무기물 절연층 표면에 구비되는 인식마크; 상기 캐비티 또는 상기 리세스부 내부로 적어도 일부가 삽입되며, 적어도 일면에 외부전극이 구비된 전자부품; 상기 무기물 절연층 상에 형성되는 유기물 재질의 제1 빌드업 절연층; 및 상기 제1 빌드업 절연층 표면에 형성되는 제2 회로 패턴층;을 포함할 수 있으며, 워피지를 종래보다 저감시키면서도 비아 및 회로 패턴 등을 효율적으로 구현할 수 있다.
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公开(公告)号：KR101442347B1
公开(公告)日：2014-09-17
申请号：KR1020120129425
申请日：2012-11-15
Applicant: 삼성전기주식회사
CPC classification number: H05K1/185 , H05K1/0231 , H05K1/0271 , H05K3/4602 , H05K2201/068
Abstract: 본 발명은 캐패시터 내장 기판에 관한 것으로, 적층코어 내부에 용량이 서로 다른 복수 개의 캐패시터를 내장하고, 이들 캐패시터가 병렬로 연결되게 함으로써, 넓은 주파수 대역에 걸쳐 임피던스를 낮게 구현함과 동시에 방열성능 및 신호전달성능을 향상시킨 캐패시터 내장 기판을 개시한다.
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公开(公告)号：KR1020140071769A
公开(公告)日：2014-06-12
申请号：KR1020120139727
申请日：2012-12-04
Applicant: 삼성전기주식회사
CPC classification number: H05K1/186 , H05K3/403 , H05K3/4602 , H05K2201/09645 , H05K2203/0228 , H05K2203/0242 , Y10T29/49139
Abstract: The present invention relates to a substrate embedding electronic component. The substrate embedding electronic component includes a cavity in which at least one insulating layer is formed; an electronic component which is partly inserted into the cavity; and a cavity plating part which is formed in a surface which faces at least one surface of the electronic component. The electrical connectivity between an external electrode and a via can be improved even when the size of the external electrode of the electronic component is smaller than an existing external electrode.
Abstract translation: 本发明涉及一种嵌入电子元件的基板。 基板嵌入式电子元件包括形成有至少一个绝缘层的空腔; 一部分插入到该腔中的电子部件; 以及形成在面向所述电子部件的至少一个表面的表面中的空腔镀敷部。 即使当电子部件的外部电极的尺寸小于现有的外部电极时，也可以提高外部电极和通孔之间的电连接性。
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公开(公告)号：KR1020140069592A
公开(公告)日：2014-06-10
申请号：KR1020120137048
申请日：2012-11-29
Applicant: 삼성전기주식회사
CPC classification number: H05K1/186 , H01L2924/15311 , H05K3/4644 , H05K3/4697 , H05K2201/10015 , H05K2201/10636 , Y02P70/611 , Y10T29/4913
Abstract: The present invention relates to a substrate embedding an electronic component. The substrate embedding an electronic component comprises: a first insulating layer which includes a cavity; an electronic component inserted into the cavity and has at least one external electrode; a first metal pattern formed on the lower surface of the first insulating layer to mount the electronic component and includes at least one guide hole to expose a portion of the external electrode; a second insulating layer formed on the lower surface of the first insulating layer and covers the first metal pattern; a first circuit pattern formed on the lower surface of the second insulating layer; and a first via which electrically connects the external electrode exposed by the guide hole and the first circuit pattern. The electrical connectivity between the external electrode and the via can be improved even when the size of the external electrode of the electronic component becomes smaller than the conventional size.
Abstract translation: 本发明涉及嵌入电子部件的基板。 嵌入电子部件的基板包括：第一绝缘层，其包括空腔; 插入到所述腔中并具有至少一个外部电极的电子部件; 第一金属图案，形成在所述第一绝缘层的下表面上以安装所述电子部件，并且包括至少一个引导孔以暴露所述外部电极的一部分; 第二绝缘层，形成在所述第一绝缘层的下表面上并覆盖所述第一金属图案; 形成在所述第二绝缘层的下表面上的第一电路图案; 以及第一通孔，其将由引导孔暴露的外部电极和第一电路图案电连接。 即使当电子部件的外部电极的尺寸变得比常规尺寸小时，也可以提高外部电极和通孔之间的电连接性。
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Patent Agency Ranking
公开(公告)号：KR1020130078107A
公开(公告)日：2013-07-10
申请号：KR1020110146877
申请日：2011-12-30
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/04105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/00012
Abstract: PURPOSE: A component-integrated printed circuit board and a manufacturing method thereof are provided to form a metal core to integrate electric components inside and to electrically connect the metal core and the electric components to an external metal pattern through vias to discharge the heat inside. CONSTITUTION: A manufacturing method for a component-integrated printed circuit board includes a step of preparing a copper-coated laminated plate (CCL) (100); a step of forming a metal core (120) with a cavity by platting on the top surface of the copper-coated laminated plate; a step of inserting an electric component (130) into the cavity; a step of forming an insulating layer (150) between the top surface of the electric component and the top of the metal core; and a step of forming a metal layer (160) on the top of the insulating layer and forming a pattern by patterning on a foil layer (102) which is formed on the metal layer and on the bottom of the metal core.
Abstract translation: 目的：提供一种组件集成印刷电路板及其制造方法，以形成金属芯，以将电子元件集成在内部，并通过通孔将金属芯和电气元件电连接到外部金属图案，以将热量排出。 构成：组件集成印刷电路板的制造方法包括制备铜包覆层压板（CCL）（100）的步骤; 通过在铜包覆层压板的顶表面上镀层而形成具有空腔的金属芯（120）的步骤; 将电气部件（130）插入到所述空腔中的步骤; 在电气部件的上表面与金属芯的顶部之间形成绝缘层（150）的工序; 以及在绝缘层的顶部上形成金属层（160）的步骤，并且通过在形成在金属层和金属芯的底部上的箔层（102）上进行图案化而形成图案。
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公开(公告)号：KR101171280B1
公开(公告)日：2012-08-07
申请号：KR1020110007498
申请日：2011-01-25
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A method for replacing a defective unit substrate of a substrate strip is provided to efficiently replace the defective unit substrate by using a first carrier as a supporter to bond a unit substrate without defects. CONSTITUTION: A first carrier is attached to one side of a first substrate strip(S100). The first substrate strip is separated from the edge of a defective unit substrate(S200). The first substrate strip is separated from the first carrier to remove the defective unit substrate(S300). A unit substrate without defects is combined in the position to remove the defective unit substrate of the first substrate strip(S400).
Abstract translation: 目的：提供一种用于替换衬底条的缺陷单元衬底的方法，以便通过使用第一载体作为支撑体来有效地替换缺陷单元衬底，从而将单元衬底无缺陷地接合。 构成：第一载体附着在第一基片条的一侧（S100）。 第一衬底带与缺陷单元衬底的边缘分离（S200）。 将第一衬底条与第一载体分离以去除缺陷单元衬底（S300）。 没有缺陷的单元基板被组合在去除第一基板条的缺陷单元基板的位置（S400）。
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公开(公告)号：KR1020120086193A
公开(公告)日：2012-08-02
申请号：KR1020110007498
申请日：2011-01-25
Applicant: 삼성전기주식회사
Abstract: 기판스트립의 불량 단위기판 교체방법이 개시된다. 본 발명의 실시예에 따른 기판스트립의 불량 단위기판 교체방법은 일면 전체가 단위기판으로 구획되는 제1 기판스트립의 불량 단위기판을 교체하는 방법으로서, 상기 제1 기판스트립의 일면에 제1 캐리어를 부착하는 단계; 상기 제1 기판스트립과 상기 불량 단위기판의 가장자리를 분리하는 단계; 및 상기 불량 단위기판이 제거되도록 상기 제1 기판스트립과 상기 제1 캐리어를 분리하는 단계를 포함할 수 있다.
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公开(公告)号：KR1020120069452A
公开(公告)日：2012-06-28
申请号：KR1020100131006
申请日：2010-12-20
Applicant: 삼성전기주식회사
Abstract: PURPOSE: An electronic component embedded rigid-flexible printed circuit board manufacturing method is provided to easily eliminate a dummy region of a flexible region by forming the dummy region which includes a slit on the flexible region. CONSTITUTION: A base substrate(10) is prepared. A cavity is formed on the base substrate in a thickness direction. An electronic component(30) is installed inside the cavity. A first insulation layer(41) is laminated in order to fill the cavity on one side of the base substrate. A second insulation layer(50) which includes the cavity is laminated on a region for forming a flexible region. A flexible base substrate(60) is laminated on the second insulation layer. A dummy region which includes the cavity is eliminated.
Abstract translation: 目的：提供一种电子部件嵌入式刚柔柔性印刷电路板制造方法，通过在柔性区域上形成包括狭缝的虚拟区域，容易地消除柔性区域的虚拟区域。 构成：制备基底（10）。 在基底基板上沿厚度方向形成空腔。 电子部件（30）安装在腔内。 层叠第一绝缘层（41）以填充基底基板的一侧上的空腔。 包括空腔的第二绝缘层（50）层压在用于形成柔性区域的区域上。 柔性基底基板（60）层叠在第二绝缘层上。 消除了包括空腔的虚拟区域。
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公开(公告)号：KR1020120031644A
公开(公告)日：2012-04-04
申请号：KR1020100093133
申请日：2010-09-27
Applicant: 삼성전기주식회사
IPC: G01R31/3183 , G01R31/28
CPC classification number: G01R31/318536
Abstract: PURPOSE: A boundary scan test apparatus and method of an embedded substrate are provided to improve reliability of function test about the embedded substrate by processing a boundary scan test about a semiconductor chip included in the embedded substrate. CONSTITUTION: A boundary scan test arrangement of an embedded substrate comprises a plurality of embedded substrates(1), a plurality of test chips(2), and a test controller(3). The embedded substrate includes a semiconductor chip which becomes an object for test. The test chip processes a boundary scan test about the semiconductor chip included in the embedded substrate. The test controller controls the test chip. The plurality of test chips is formed into a chain shape in which a test input terminal is connected to a test output terminal. A first probe is connected to a contact point of one side of the embedded substrate. A second probe is connected to a contact point of the other side of the embedded substrate.
Abstract translation: 目的：提供嵌入式基板的边界扫描测试装置和方法，通过处理包括在嵌入式基板中的半导体芯片的边界扫描测试来提高嵌入式基板的功能测试的可靠性。 构成：嵌入式基板的边界扫描测试装置包括多个嵌入式基板（1），多个测试芯片（2）和测试控制器（3）。 嵌入式基板包括成为测试对象的半导体芯片。 测试芯片对包含在嵌入式衬底中的半导体芯片进行边界扫描测试。 测试控制器控制测试芯片。 多个测试芯片形成为测试输入端子连接到测试输出端子的链状。 第一探针连接到嵌入式基板的一侧的接触点。 第二探针连接到嵌入式基板的另一侧的接触点。
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