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公开(公告)号：KR101913387B1
公开(公告)日：2018-10-30
申请号：KR1020120030245
申请日：2012-03-23
Applicant: 삼성전자주식회사
IPC: H01L21/331 , H01L29/737
CPC classification number: H01L21/268 , H01L21/28575 , H01L21/3245 , H01L29/2003 , H01L29/452 , H01L29/517 , H01L29/66462
Abstract: Ⅲ족질화물이종접합구조소자의선택적저온오믹콘택형성방법이제공된다. 선택적저온오믹콘택형성방법은Ⅲ족질화물이종접합층이형성되고오믹콘택영역이정의된에피기판상에도전막과상기도전막의상부형성되거나상기도전막과상기Ⅲ족질화물이종접합층의사이에개재된캐핑막을형성하되, 상기캐핑막은상기오믹콘택영역또는비오믹콘택영역중 어느한 영역에만형성하고, 상기기판의전면에 750℃이하의온도로레이저어닐링, 유도가열, 또는이들의조합을적용하여상기오믹콘택영역에선택적으로오믹콘택을완성하는것을포함한다.
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公开(公告)号：KR101813178B1
公开(公告)日：2017-12-29
申请号：KR1020110061798
申请日：2011-06-24
Applicant: 삼성전자주식회사 , 경북대학교 산학협력단
IPC: H01L29/778 , H01L21/335
Abstract: 이차원전자가스를갖는적층구조물, 이를포함하는반도체소자및 이들의제조방법에관해개시되어있다. 개시된적층구조물의형성방법은제1물질층을형성하는단계, 상기제1물질층을열처리하는단계및 상기제1물질층상에상기제1물질층에이차원전자가스(two-dimensional electron gas)(2DEG)를유발시키는제2물질층을형성하는단계를포함할수 있다. 상기제1물질층의열처리는상기제1물질층의표면조도(surface roughness) 및/또는표면상태(surface states)를증가시키는조건으로수행할수 있다. 위와같은방법으로형성된적층구조물상에반도체소자를제조할수 있다.
Abstract translation: 具有二维电子气的堆叠结构，包括该堆叠结构的半导体器件及其制造方法。 所公开的形成堆叠结构的方法包括：形成第一材料层;对第一材料层进行热处理;以及在第一材料层上沉积二维电子气（2DEG） Lt是第二材料层。 第一材料层的热处理可以在增加第一材料层的表面粗糙度和/或表面状态的条件下进行。 可以在由上述方法形成的叠层结构上制造半导体器件。
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公开(公告)号：KR101720589B1
公开(公告)日：2017-03-30
申请号：KR1020100098995
申请日：2010-10-11
Applicant: 삼성전자주식회사
IPC: H01L29/778
CPC classification number: H01L29/7786 , H01L29/2003 , H01L29/201 , H01L29/66462
Abstract: E-mode를갖는고 전자이동도트랜지스터및 그제조방법에관해개시되어있다. 일실시예에의한 E-mode를갖는 HEMT는기판상에형성된버퍼층, 상기버퍼층상에형성되고, 2DEG를포함하는채널층, 상기채널층상에형성된배리어층및 상기배리어층상에형성된게이트전극과소스및 드레인전극을포함하고, 상기배리어층은상기채널층의상기게이트전극에대응하는영역에서분극율의변화를갖는층을포함한다.
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公开(公告)号：KR101626463B1
公开(公告)日：2016-06-02
申请号：KR1020100018068
申请日：2010-02-26
Applicant: 삼성전자주식회사
IPC: H01L29/778
CPC classification number: H01L29/402 , H01L29/0891 , H01L29/66462 , H01L29/7786
Abstract: 고전자이동도트랜지스터(HEMT)의제조방법이개시되어있다. 본발명의일 실시예에의한 HEMT의제조방법은기판상에격자상수가다른제1 및제2 물질층을형성한다음, 상기제2 물질층상에소스, 드레인및 게이트를형성하고, 상기게이트와상기드레인사이의상기제2 물질층을이종물질층으로변화시키거나상기제2 물질층의두께를변화시키거나상기제2 물질층상에 p형반도체층을형성한다. 상기소스, 드레인및 게이트는상기제2 물질층과직접접촉될수 있다. 상기제2 물질층의변화는상기게이트와상기드레인사이의전체영역또는상기게이트에인접한일부영역에서나타날수 있다. 상기 p형반도체층은상기게이트와상기드레인사이의상기제2 물질층의상부면전체또는상기게이트에인접한일부영역상에형성할수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020140118012A
公开(公告)日：2014-10-08
申请号：KR1020130033089
申请日：2013-03-27
Applicant: 삼성전자주식회사
IPC: H01L29/861 , H01L29/778
CPC classification number: H01L29/778 , H01L29/1608 , H01L29/402 , H01L29/7787
Abstract: Disclosed are a power device chip and a method of manufacturing the same. A power device chip according to an embodiment includes unit power elements which are separated into sectors, a first pad connected to a first electrode of the unit power elements, and a second pad connected to a second electrode of the unit power elements. At least one of the first and the second pad is separated into several parts which are equal to the number of the sectors. In the power chip, the unit power element can be a diode. The unit power element can further include a third electrode. The third electrode can be connected to a third pad. In this case, the unit power element can be an HEMT. A pad connected to a defect sector among the separated pads is automatically removed in a bonding process.
Abstract translation: 公开了功率器件芯片及其制造方法。 根据实施例的功率器件芯片包括分离成扇区的单元功率元件，连接到单元功率元件的第一电极的第一焊盘和连接到单元功率元件的第二电极的第二焊盘。 第一和第二垫中的至少一个被分成几个等于扇区数的部分。 在功率芯片中，单位功率元件可以是二极管。 单元功率元件还可以包括第三电极。 第三电极可以连接到第三焊盘。 在这种情况下，单元功率元件可以是HEMT。 连接到分离的焊盘之间的缺陷扇区的焊盘在焊接过程中被自动去除。
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公开(公告)号：KR1020140074160A
公开(公告)日：2014-06-17
申请号：KR1020130033668
申请日：2013-03-28
Applicant: 삼성전자주식회사
IPC: H01L29/778 , H01L21/335
Abstract: A high electron mobility transistor is disclosed. The disclosed high electron mobility transistor includes a channel supply layer which generates a 2D electronic gas in a channel layer, a first gate electrode which is prepared between a source electrode and a drain electrode, at least one second gate electrode which is prepared between the source electrode and the first gate electrode, and a gate electrode receiving part which is formed on the channel supply layer and receives the first and the second gate electrode.
Abstract translation: 公开了一种高电子迁移率晶体管。 所公开的高电子迁移率晶体管包括在沟道层中产生2D电子气体的通道供应层，准备在源极和漏极之间的第一栅电极，至少一个第二栅电极，其在源 电极和第一栅电极，以及形成在沟道供给层上并接收第一和第二栅电极的栅电极接收部。
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公开(公告)号：KR1020140067524A
公开(公告)日：2014-06-05
申请号：KR1020120134866
申请日：2012-11-26
Applicant: 삼성전자주식회사
CPC classification number: H01L24/81 , H01L24/02 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/73 , H01L24/94 , H01L29/4175 , H01L29/7786 , H01L2224/02372 , H01L2224/0239 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05567 , H01L2224/0603 , H01L2224/06102 , H01L2224/11002 , H01L2224/11334 , H01L2224/1184 , H01L2224/11845 , H01L2224/131 , H01L2224/1403 , H01L2224/16235 , H01L2224/73251 , H01L2224/81005 , H01L2224/94 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/00 , H01L2224/11 , H01L2224/81 , H01L2924/014 , H01L2924/01079 , H01L2924/00014 , H01L2924/0105 , H01L2224/023 , H01L2224/13
Abstract: Disclosed is a wafer level packaging method of a power device. The disclosed wafer level packaging method of a power device includes a step of preparing a wafer which has an upper part where nitride power devices having electrodes are formed, a step of forming a polymer layer on the nitride power devices, a step of exposing each electrode in the polymer layer, a step of forming a solder bump on the exposed electrode, a step of forming a molding layer which covers the solder bump on the polymer layer, a step of removing the wafer and exposing the solder bump.
Abstract translation: 公开了功率器件的晶片级封装方法。 所公开的功率器件的晶片级封装方法包括制备具有上部形成有具有电极的氮化物功率器件的晶片的步骤，在氮化物功率器件上形成聚合物层的步骤， 在聚合物层中，在暴露的电极上形成焊料凸块的步骤，形成覆盖聚合物层上的焊料凸块的模塑层的步骤，去除晶片并暴露焊料凸块的步骤。
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公开(公告)号：KR1020140045843A
公开(公告)日：2014-04-17
申请号：KR1020120112092
申请日：2012-10-09
Applicant: 삼성전자주식회사
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/778 , H01L29/1066 , H01L29/2003 , H01L29/41766 , H01L29/66431 , H01L29/66462 , H01L29/7786
Abstract: Disclosed are a high electron mobility transistor (HEMT) and a method of fabricating the same. The disclosed HEMT includes a channel layer; a channel supply layer formed on the channel layer and having an energy bandgap greater than that of the channel layer; a P-type semiconductor layer formed on the channel supply layer and having an energy bandgap different from that of the channel supply layer; a gate electrode formed on the P-type semiconductor layer; and source and drain electrodes formed at both sides of the gate electrode while being spaced apart from each other. The P-type semiconductor layer includes a hole injection layer formed on the channel supply layer to supply holes to at least one among the channel layer and the channel supply layer in an on state and a depletion forming layer formed at a portion of the hole injection layer and having a doping concentration different from the doping concentration of the hole injection layer.
Abstract translation: 公开了高电子迁移率晶体管（HEMT）及其制造方法。 所公开的HEMT包括通道层; 沟道供应层，其形成在沟道层上并具有比沟道层大的能带隙; 形成在所述沟道供给层上并具有与所述沟道供给层不同的能带隙的P型半导体层; 形成在P型半导体层上的栅电极; 以及形成在栅极两侧的源极和漏极，同时彼此间隔开。 P型半导体层包括形成在沟道供给层上的空穴注入层，以在导通状态下向沟道层和沟道供给层中的至少一个提供空穴，并且在空穴注入的一部分形成有耗尽形成层 并且具有不同于空穴注入层的掺杂浓度的掺杂浓度。
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公开(公告)号：KR1020140042469A
公开(公告)日：2014-04-07
申请号：KR1020120109266
申请日：2012-09-28
Applicant: 삼성전자주식회사
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/2003 , H01L29/205 , H01L29/66204 , H01L29/66325 , H01L29/861
Abstract: A power switching device and a method of manufacturing the same are disclosed. A power switching device according to one embodiment of the present invention includes a channel formation layer which is formed on a substrate and includes a 2D electron gas (2DEG), a channel supply layer which generates the 2DEG in the channel formation layer, a cathode which touches one side of the channel supply layer, and an anode which touches the other side of the channel supply layer. The channel formation layer includes depletion regions which are arranged with a stripe shape. Spaces between the depletion regions are non-depletion regions. P-GaN layers exist on the channel supply layer. The P-GaN layers correspond to the depletion regions one-to-one.
Abstract translation: 公开了电力开关装置及其制造方法。 根据本发明的一个实施例的功率开关器件包括形成在衬底上并包括2D电子气体（2DEG）的通道形成层，在沟道形成层中产生2DEG的沟道供应层，阴极， 触摸通道供应层的一侧，以及接触通道供应层的另一侧的阳极。 通道形成层包括排列成条状的耗尽区域。 耗尽区之间的空位是非耗尽区。 在沟道供应层上存在P-GaN层。 P-GaN层对应于耗尽区域一对一。
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