公开(公告)号：KR1020130098685A

公开(公告)日：2013-09-05

申请号：KR1020120020402

申请日：2012-02-28

Applicant: 삼성전자주식회사

Inventor： 김종연 ,  민태홍 ,  고영권 ,  조태제

IPC: H01L23/48 ,  H01L23/60

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: PURPOSE: A semiconductor package is provided to improve reliability by performing the EDS test of a test pad when a top chip is laminated. CONSTITUTION: A first chip (100) is divided into a chip area and a scribe area which is arranged on the edge of the chip area. The first chip includes a main TSV (130) and an integrated circuit part formed on the chip area. A second chip (200) is bonded to the upper side of the first chip. A dummy line (185) is extended from the chip area to the scribe area of the first chip. A dummy TSV is formed on the scribe area of the first chip. A test pad is formed on a protection layer (160) which is located on the scribe area.

Abstract translation: 目的：提供半导体封装以通过在顶层芯片层叠时执行测试焊盘的EDS测试来提高可靠性。 构成：第一芯片（100）被分成芯片区域和布置在芯片区域的边缘上的划线区域。 第一芯片包括形成在芯片区域上的主TSV（130）和集成电路部分。 第二芯片（200）接合到第一芯片的上侧。 伪线（185）从芯片区域延伸到第一芯片的划线区域。 虚拟TSV形成在第一芯片的划线区域上。 测试垫形成在位于划线区域上的保护层（160）上。

公开(公告)号：KR1020130082314A

公开(公告)日：2013-07-19

申请号：KR1020120003454

申请日：2012-01-11

Applicant: 삼성전자주식회사

Inventor： 최윤석 ,  조태제

IPC: H01L23/48 ,  H01L23/12 ,  H01L21/60

CPC classification number: H01L25/074 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/24 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05552

Abstract: PURPOSE: A semiconductor package is provided to reduce the limit of the size and sequence of stacked semiconductor chips by applying a chip stack structure using a TSV. CONSTITUTION: A chip stack part (200) is mounted on a substrate (110) with a flip chip type. The chip stack part includes a first chip (220), a second chip (230), a connecting member (240), and an inner sealing material (260). The first chip includes a body part (221), an inner chip pad (225), and a TSV (226). A second semiconductor chip (320) and a third semiconductor chip (420) are successively stacked on the upper side of the chip stack part. A signal transmitting medium (170) connects the second semiconductor chip and the third semiconductor chip to the substrate.

Abstract translation: 目的：提供半导体封装以通过使用TSV施加芯片堆叠结构来减小堆叠半导体芯片的尺寸和顺序的限制。 构成：芯片堆叠部分（200）以倒装芯片类型安装在基板（110）上。 芯片堆叠部分包括第一芯片（220），第二芯片（230），连接构件（240）和内部密封材料（260）。 第一芯片包括主体部分（221），内芯片焊盘（225）和TSV（226）。 第二半导体芯片（320）和第三半导体芯片（420）依次堆叠在芯片堆叠部分的上侧。 信号传输介质（170）将第二半导体芯片和第三半导体芯片连接到基板。

公开(公告)号：KR1020130058401A

公开(公告)日：2013-06-04

申请号：KR1020110124392

申请日：2011-11-25

Applicant: 삼성전자주식회사

Inventor： 임윤혁 ,  김원근 ,  조태제 ,  박결

IPC: H01L23/28 ,  H01L23/34

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10126 ,  H01L2224/10156 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83007 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83887 ,  H01L2224/83888 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor package is provided to secure structure stability by controlling the filler distribution between a substrate and a semiconductor chip in an underfill process. CONSTITUTION: A semiconductor chip(210) is formed on a substrate. A heat generation pattern(118,218) is formed between the substrate and the semiconductor chip. The heat generation pattern generates heat. An underfill resin(310) is underfilled between the substrate and the semiconductor chip. The underfill resin includes a filler.

Abstract translation: 目的：提供半导体封装以通过在底部填充工艺中控制衬底和半导体芯片之间的填料分布来确保结构稳定性。 构成：在基板上形成半导体芯片（210）。 在衬底和半导体芯片之间形成发热图案（118,218）。 发热模式产生热量。 衬底和半导体芯片之间底层填充树脂310。 底部填充树脂包括填料。

公开(公告)号：KR1020130027628A

公开(公告)日：2013-03-18

申请号：KR1020110062479

申请日：2011-06-27

Applicant: 삼성전자주식회사

Inventor： 정세영 ,  정태경 ,  조태제 ,  박상식

IPC: H01L23/48 ,  H01L23/12 ,  H01L21/60

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06155 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: PURPOSE: A laminated semiconductor device is provided to reduce an interval of a rewiring unit formed between laminated semiconductor chips by forming a scribe lane part with a step with a semiconductor chip on one side of the semiconductor chip and forming the rewiring unit on a scribe lane part. CONSTITUTION: A plurality of semiconductor chips(100,200,300) are vertically laminated and are arranged on a substrate(10). A scribe lane part(120,220,320) is formed on one side of the semiconductor chip to have a step with the semiconductor chip. A rewiring part(160,260,360) is formed on the scribe lane part and the semiconductor chip. The rewiring part covers a pad(50) formed on the semiconductor chip. A signal connection member(500) is formed on one side of the semiconductor chip and electrically connects the rewiring part. A bonding layer(250) is formed on the semiconductor chip and the rewiring part to bond another semiconductor chip.

Abstract translation: 目的：提供一种层叠半导体器件，通过在半导体芯片的一侧上形成具有半导体芯片的步骤的划线路部分，并在切割线上形成重新布线单元，来减小层叠半导体芯片之间形成的重新布线单元的间隔 部分。 构成：将多个半导体芯片（100,200,300）垂直层叠并配置在基板（10）上。 在半导体芯片的一侧上形成划线路部分（120,220,320）以与半导体芯片形成台阶。 重划线部分（160,260,360）形成在划线路部分和半导体芯片上。 再布线部分覆盖形成在半导体芯片上的焊盘（50）。 信号连接构件（500）形成在半导体芯片的一侧，并电连接重新布线部分。 在半导体芯片和重新布线部分上形成结合层（250）以将另一半导体芯片接合。

公开(公告)号：KR1020090027325A

公开(公告)日：2009-03-17

申请号：KR1020070092462

申请日：2007-09-12

Applicant: 삼성전자주식회사

Inventor： 임충빈 ,  조태제

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L2224/48227 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331

Abstract: A semiconductor package and semiconductor module having the same are provided to arrange the pads in the upper surface of the insulating substrate and to use the land of the circuit board and pads of the semiconductor package as the outer connector. The insulating substrate(120) is adhered on the semiconductor chip. The first bond finger(130) is arranged on the edge of the upper side of the insulating substrate. First bond fingers are electrically connected to the semiconductor chip. The pad(140) is arranged on the central part of the upper side of the insulating substrate. Pads are electrically connected to first bond fingers. The first bond fingers can have the rectangular shape.

Abstract translation: 提供具有该半导体封装和半导体模块的半导体封装和半导体模块以在绝缘基板的上表面中布置焊盘并且使用电路板的焊盘和半导体封装的焊盘作为外部连接器。 绝缘基板（120）粘附在半导体芯片上。 第一接合指（130）布置在绝缘基板的上侧的边缘上。 第一接合指状物电连接到半导体芯片。 衬垫（140）布置在绝缘衬底的上侧的中心部分上。 垫片电连接到第一粘合指状物。 第一粘结指状物可具有矩形形状。

公开(公告)号：KR1020060074796A

公开(公告)日：2006-07-03

申请号：KR1020050021180

申请日：2005-03-14

Applicant: 삼성전자주식회사

Inventor： 권흥규 ,  조태제 ,  장경래

IPC: H01L23/12

CPC classification number: H01L24/49 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a semiconductor device package in which instability of a bonding wire that may occur when a plurality of semiconductor chips are stacked is prevented and which obtains a light, thin and small structure. The semiconductor device package includes a substrate having a plurality of substrate pads on a top surface of the semiconductor device package and includes a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips have a chip pad electrically connected to a common pin, e.g., to which a common signal may be concurrently applied to each of the semiconductor chips. An interposer chip, also stacked on the substrate, has a connecting wire electrically connected to the chip pad, the common pin of each of the semiconductor chips being thereby electrically coupled at the connecting wire via the chip pad, and the connecting wire being thereby electrically connected to the substrate pad.

Abstract translation: 提供一种半导体器件封装，其中防止了当堆叠多个半导体芯片时可能发生的接合线的不稳定性，并获得轻薄的结构。 半导体器件封装包括在半导体器件封装的顶表面上具有多个衬底焊盘并且包括堆叠在衬底上的多个半导体芯片的衬底。 每个半导体芯片具有电连接到公共引脚的芯片焊盘，例如可以将公共信号同时施加到每个半导体芯片。 也堆叠在基板上的插入式芯片具有电连接到芯片焊盘的连接线，因此每个半导体芯片的公共引脚通过芯片焊盘在连接线处电耦合，并且连接线由此电连接 连接到基板垫。

公开(公告)号：KR100459820B1

公开(公告)日：2005-07-07

申请号：KR1019970047425

申请日：1997-09-13

Applicant: 삼성전자주식회사

Inventor： 안은철 ,  송영재 ,  조태제

IPC: H01L23/28

Abstract: 본 발명에 의한 칩 스케일 패키지(CSP) 및 그 제조방법은, 중앙부에는 관통 홀이 형성되고, 그 주변의 기판 하부면이 소정 두께 리세스된 구조를 갖는 금속 기판을 이용하여 CSP를 제조하도록 이루어져, 첫째, 본딩 패드와 금속 배선이 기판의 리세스된 면에서 금속 와이어에 의해 전기적으로 연결되므로, 용이한 와이어 본딩 작업이 가능하게 되고 둘째, 성형수지가 금속 기판의 리세스된 부분을 포함한 관통 홀 내부에만 채워지도록 봉지되므로, 패키지의 박형화·소형화로 인해 솔더 볼의 피치 및 사이즈가 점차 미세화될 경우에도 포팅 공정 진행의 어려움을 해소할 수 있게 되며 셋째, 제품 조립후 열팽창 계수 차이로 인해 야기되던 CSP의 휨 현상을 방지할 수 있게 되므로, 솔더 볼의 코플레이너리티(coplanarity)를 확보할 수 있게 되고 넷째, 반도체 칩과 솔 더 볼 사이에 금속 기판이 놓여지므로, CSP의 열방출 능력을 향상시킬 수 있게 된다.

公开(公告)号：KR1020010026512A

公开(公告)日：2001-04-06

申请号：KR1019990037865

申请日：1999-09-07

Applicant: 삼성전자주식회사

Inventor： 안은철 ,  조태제

IPC: H01L23/02

CPC classification number: H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PURPOSE: A multichip package is provided to allow the use of various kinds of chips regardless of the size of the chip or the position of the bonding pads. CONSTITUTION: The multichip package(200) includes two or more chips(210,220) different in size and having different bonding pads(215,225) in position. The package(200) further includes a base substrate(140) having slits formed therein correspondingly to the position of the bonding pads(215,225). The base substrate(140) has circuitry patterns formed on one surface thereof, connecting pads(144) each coupled to one end of each circuitry pattern, and solder ball pads(148) each coupled to the other end of each circuitry pattern. The connecting pads(144) are electrically connected to the bonding pads(215,225) by wires(150) through the slits, and the solder ball pads(148) are joined to solder balls(180). The chips(210,220) are attached, in a stack or alternatively side by side, to the opposite surface of the base substrate(140) by an adhesive(130). The chips(210,220) are embedded in a mold body(170), and the wires(150) and the connecting pads(144) are coated with a coating resin(160).

Abstract translation: 目的：提供多芯片封装以允许使用各种芯片，而不考虑芯片的尺寸或焊盘的位置。 构成：多芯片封装（200）包括两个或更多个尺寸不同的芯片（210,220），并具有位置不同的焊盘（215,225）。 所述封装（200）还包括基板（140），所述基板（140）具有与所述焊盘（215,225）的位置对应的狭缝。 基底衬底（140）具有在其一个表面上形成的电路图案，每个耦合到每个电路图案的一端的连接焊盘（144）和每个耦合到每个电路图案的另一端的焊球焊盘（148）。 连接焊盘（144）通过导线（150）通过狭缝电连接到接合焊盘（215,225），并且焊球焊盘（148）与焊球（180）接合。 芯片（210,220）以堆叠方式或可选地并排地通过粘合剂（130）附接到基底基板（140）的相对表面。 芯片（210,220）嵌入在模具主体（170）中，并且电线（150）和连接焊盘（144）涂覆有涂覆树脂（160）。

公开(公告)号：KR1020000003000A

公开(公告)日：2000-01-15

申请号：KR1019980024058

申请日：1998-06-25

Applicant: 삼성전자주식회사

Inventor： 목승곤 ,  조태제

IPC: H01L23/28

Abstract: PURPOSE: A BGA package is provided to enhance the yield rate by preventing the defect of being bent and to prevent the damage of a semiconductor chip. CONSTITUTION: A BGA package comprises: more than one of semiconductor chip(310) having bonding pads; a substrate(220) having the semiconductor chip inside; solder balls(350) formed on a certain area of the substrate; dummy solder balls(370) having its surface coat to be electrically insulated; and an insulating tape formed in the same height as the solder balls.

Abstract translation: 目的：提供BGA封装，通过防止弯曲的缺陷并防止半导体芯片的损坏来提高成品率。 构成：BGA封装包括：多于一个具有接合焊盘的半导体芯片（310） 内部具有半导体芯片的基板（220） 形成在基板的某一区域上的焊球（350） 其表面涂层被电绝缘的虚拟焊球（370） 以及形成与焊球相同高度的绝缘带。

公开(公告)号：KR1019980033976A

公开(公告)日：1998-08-05

申请号：KR1019960051873

申请日：1996-11-04

Applicant: 삼성전자주식회사

Inventor： 송영재 ,  조태제 ,  안승호 ,  송영희

IPC: H01L23/28

Abstract: 본 발명은 TSOP 소자에 관한 것이며, 패키지 몸체 성형시 성형수지의 흐름차에 의한 불량, 외부리드 솔더 접합부의 크랙, 센타 패드형 칩에 일반 리드 프레임을 적용할 때 본딩 와이어가 반도체 칩과 접촉하는 불량 등을 방지하기 위하여 리드 프레임 패드가 칩의 활성면에 접착성 물질에 의해 부착되는데, 칩의 전극 패드는 개방될 수 있도록 부착되며 리드 프레임 패드는 단차 가공이 되지 않고 리드 프레임 리드가 동일한 높이를 가지도록 함으로써 금속 와이어가 본딩되는 칩의 전극 패드는 와이어가 본딩되는 리드보다 높이가 낮은 위치에 있고 외부 리드는 패키지 몸체의 상부에서 돌출된다.