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公开(公告)号：KR1020070025859A
公开(公告)日：2007-03-08
申请号：KR1020050082450
申请日：2005-09-05
Applicant: 삼성전자주식회사
CPC classification number: H01L21/02071 , C11D3/042 , C11D3/046 , C11D3/2075 , C11D11/0047 , H01L21/0206 , H01L21/28282
Abstract: Provided is a composition for cleaning a substrate, which removes polymeric residue generated by the etching of a metal layer while allowing the remaining part of the layer to leave on the substrate, and is useful for forming a gate of a semiconductor device having excellent electrical properties. The composition for cleaning a substrate comprises: a fluorine compound; inorganic acid; and deionized water. The fluorine compound is used in an amount of about 0.001-10.0 wt% and the inorganic acid is used in an amount of about 3-20 wt% based on the total weight of the composition. The fluorine compound includes HF. NH4F or a mixture thereof. The inorganic acid includes HNO3, HCl, HClO4, H2SO4, H5IO6 or a mixture thereof. The composition optionally further comprises an organic acid of about 50 wt% or less, based on the total weight of the composition.
Abstract translation: 本发明提供一种清洗基板的组合物，其除去通过蚀刻金属层而产生的聚合物残留物，同时允许该层的剩余部分留在基板上，并且可用于形成具有优异电性能的半导体器件的栅极 。 用于清洗基材的组合物包括：氟化合物; 无机酸; 和去离子水。 氟化合物的使用量为约0.001-10.0重量％，无机酸的用量为组合物总重量的约3-20重量％。 氟化合物包括HF。 NH4F或其混合物。 无机酸包括HNO 3，HCl，HClO 4，H 2 SO 4，H 5 O 6或其混合物。 组合物任选地还包含基于组合物总重量的约50重量％或更少的有机酸。
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公开(公告)号：KR1020060112450A
公开(公告)日：2006-11-01
申请号：KR1020050034914
申请日：2005-04-27
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11543 , H01L21/28273
Abstract: A method for fabricating a flash memory with a U-type floating gate is provided to increase the area of an intergate dielectric without increasing a cell size by making a floating gate have an upper surface of a U type. Isolation layers(131) are formed on a substrate(110) wherein the upper surface and both lateral surfaces of the isolation layers protrude from the surface of the substrate. A tunnel oxide layer(140) is formed on the substrate between the isolation layers. A conductive layer is formed on the tunnel oxide layer, having a thickness that doesn't fill a gap between the isolation layers. A polishing sacrificial layer and a conductive layer are formed on the conductive layer. The polishing sacrificial layer and the conductive layer on the isolation layer are eliminated to form an U-typed floating gate(145a) self-aligned between the isolation layer while a polishing sacrificial layer pattern(150a) is left on the floating gate. By using the polishing sacrificial layer pattern as a mask, the isolation layers are recessed to expose both sidewalls of the floating gate. The polishing sacrificial layer pattern is selectively removed with respect to the floating gate to expose the upper surface of the floating gate. The conductive layer is made of a doped polysilicon layer. The polishing sacrificial layer is made of a silicon germanium layer.
Abstract translation: 提供了一种用U型浮动栅极制造闪速存储器的方法，通过使浮动栅极具有U型的上表面来增加隔间栅极电介质的面积，而不增加单元尺寸。 隔离层（131）形成在基板（110）上，其中隔离层的上表面和两个侧表面从基板的表面突出。 在隔离层之间的衬底上形成隧道氧化物层（140）。 在隧道氧化物层上形成导电层，其厚度不填充隔离层之间的间隙。 在导电层上形成抛光牺牲层和导电层。 消除了抛光牺牲层和隔离层上的导电层，以形成在隔离层之间自对准的U型浮动栅极（145a），同时抛光牺牲层图案（150a）留在浮动栅极上。 通过使用抛光牺牲层图案作为掩模，隔离层凹入以暴露浮动栅极的两个侧壁。 相对于浮动栅极选择性地去除抛光牺牲层图案以暴露浮动栅极的上表面。 导电层由掺杂多晶硅层制成。 抛光牺牲层由硅锗层制成。
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Patent Agency Ranking
公开(公告)号：KR1020060016631A
公开(公告)日：2006-02-22
申请号：KR1020040065144
申请日：2004-08-18
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L21/0206 , H01L21/30604
Abstract: 반도체 장치의 세정 방법을 제공한다. 이 방법은 반도체기판 상에 하부 구조체를 형성하고, 상기 하부 구조체가 형성된 결과물 상에 층간절연막을 형성하고, 상기 층간절연막을 패터닝하여 소정영역들에서 상기 하부 구조체의 상부면을 노출시키는 개구부들을 형성한 후, 상기 개구부들이 형성된 결과물을 세정하는 단계를 포함한다. 이때, 상기 세정 단계는 암모니아 희석액 및 불소 함유 세정액 중의 적어도 한가지를 사용하는 제 1 세정 단계 및 불산을 사용하는 제 2 세정 단계를 포함한다.
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公开(公告)号：KR1020060012513A
公开(公告)日：2006-02-08
申请号：KR1020040061227
申请日：2004-08-03
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/306 , C23F1/44
CPC classification number: C23F1/28 , B82Y25/00 , B82Y40/00 , C23F1/16 , C23F1/26 , C23F1/44 , H01F41/308 , H01F41/34 , H01L21/32134 , H01L43/12
Abstract: 식각 용액 및 이를 이용한 자기 기억 소자의 형성 방법을 제공한다. 식각 용액은 순수(Deionized water) 및 유기산을 포함한다. 유기산은 카르복실기와 수산기를 갖는다. 유기산은 상기 순수의 중량 대비 0.05중량% 내지 35중량%이다.
Abstract translation: 以及使用其形成磁存储元件的方法。 蚀刻溶液包括去离子水和有机酸。 有机酸具有羧基和羟基。 基于纯水的重量，有机酸为0.05重量％至35重量％。
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公开(公告)号：KR100546363B1
公开(公告)日：2006-01-26
申请号：KR1020030056009
申请日：2003-08-13
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L28/91 , H01L27/10852 , Y10S438/978
Abstract: 본원은 인접하는 스토리지 노드 전극간의 전기적 결함을 방지할 수 있는 반도체 메모리 소자 및 그 제조방법을 개시한다. 개시된 본 발명은 반도체 기판상에 전극 영역이 한정된 몰드 산화막을 형성한다음, 상기 전극 영역내에 바닥부 및 측벽부를 갖는 스토리지 노드 전극 및 상기 전극 내부의 공간을 충진하는 버퍼 산화막을 형성한다. 그후, 상기 몰드 산화막 및 버퍼 산화막의 전체 두께의 일부분을 건식 식각하여 상기 스토리지 노드 전극의 측벽부의 일부를 노출시킨다음, 상기 노출된 스토리지 노드 전극의 측벽부를 소정 폭만큼 선택적으로 식각한다. 그후, 상기 몰드 산화막 및 버퍼 산화막을 건식 식각하는 단계와, 이에 의해 노출되는 스토리지 노드 전극을 식각하는 단계를 반복 수행하여, 상기 몰드 산화막 및 버퍼 산화막을 제거한다.
콘케이브, 스토리지 노드, 무수 HF-
公开(公告)号：KR1020050018074A
公开(公告)日：2005-02-23
申请号：KR1020030056009
申请日：2003-08-13
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L28/91 , H01L27/10852 , Y10S438/978
Abstract: PURPOSE: A semiconductor memory device with a storage node of a concave type is provided to reduce the danger of a bridge and leaning and extend the height of a storage node by making a storage node of a concave type have a sidewall part that becomes narrower as it goes to its upper part and has a cross section shape symmetrical with respect to its center. CONSTITUTION: A semiconductor substrate(100) is prepared. An interlayer dielectric(110) is formed on the semiconductor substrate, including a plurality of contact plugs. A plurality of storage nodes are formed on the interlayer dielectric to come in contact with each contact plug. The storage node has a bottom part directly contacting the contact plug and a sidewall part extending from both ends of the bottom part to a direction vertical to the surface of the interlayer dielectric. The width of the sidewall part becomes narrower as it goes to its upper part. The sidewall part is bilaterally symmetrical with respect to the center line in the sidewall part such that the center line vertically bisects the sidewall part with respect to the surface of the substrate.
Abstract translation: 目的：提供一种具有凹型存储节点的半导体存储器件，以通过使凹型存储节点具有变窄的侧壁部分来减小桥梁的危险性并且倾斜并延长存储节点的高度 它到达其上部并且具有相对于其中心对称的横截面形状。 构成：制备半导体衬底（100）。 在半导体衬底上形成层间电介质（110），包括多个接触插塞。 在层间电介质上形成多个存储节点以与每个接触插塞接触。 存储节点具有直接接触接触插塞的底部和从底部的两端延伸到垂直于层间电介质的表面的方向的侧壁部分。 侧壁部分的宽度随着其上部变窄而变窄。 侧壁部分相对于侧壁部分中的中心线是双边对称的，使得中心线相对于基板的表面垂直平分侧壁部分。
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公开(公告)号：KR1020050014440A
公开(公告)日：2005-02-07
申请号：KR1020030053077
申请日：2003-07-31
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76897 , H01L21/31144 , H01L21/32134 , H01L21/32137 , H01L21/76802 , H01L23/485 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A method for fabricating a semiconductor device using a polysilicon etch mask is provided to form an etch profile of a desired type without generating the same striation as photoresist by using a polysilicon layer pattern as an etch mask. CONSTITUTION: An interlayer dielectric is formed on a semiconductor substrate. A polysilicon layer pattern is formed on the interlayer dielectric. The interlayer dielectric is etched to form a contact hole by using the polysilicon layer pattern as an etch mask. The polysilicon layer pattern is eliminated by an etch process in which etch selectivity is high with respect to the interlayer dielectric and the etch uniformity with respect to the front surface of a wafer is smaller than 3 percent. The contact hole is filled with a conductive material to form a contact(350).
Abstract translation: 目的：提供使用多晶硅蚀刻掩模制造半导体器件的方法，以通过使用多晶硅层图案作为蚀刻掩模而形成所需类型的蚀刻轮廓，而不产生与光致抗蚀剂相同的条纹。 构成：在半导体衬底上形成层间电介质。 在层间电介质上形成多晶硅层图案。 通过使用多晶硅层图案作为蚀刻掩模来蚀刻层间电介质以形成接触孔。 通过蚀刻工艺消除多晶硅层图案，其中相对于层间电介质的蚀刻选择性高，并且相对于晶片的前表面的蚀刻均匀性小于3％。 接触孔填充有导电材料以形成触点（350）。
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