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    비대칭 쇼트키 장벽을 이용한 ＴＦＥＴ 및 그 제조방법
    81.
    发明公开
    비대칭 쇼트키 장벽을 이용한 ＴＦＥＴ 및 그 제조방법 有权
    TFET使用不对称肖特基屏障及其制造方法

    公开(公告)号：KR1020110005185A

    公开(公告)日：2011-01-17

    申请号：KR1020090062763

    申请日：2009-07-09

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  김종필

    IPC: H01L29/812 ,  H01L21/338

    Abstract: PURPOSE: A tunneling field effect transistor(TFET) and a method for manufacturing the same are provided to reduce the length of a channel to be less than or equal to nano-scale sizes using a self-aligned process and a sidewall process. CONSTITUTION: A source(14) and a drain(12) are formed on the silicon layer of a silicon-on-insulator substrate to be spaced apart in a pre-set interval. The source is formed based on metal silicide. The drain is formed based on an n+ doping layer. A gate insulating layer(20) is formed on a channel region and the drain. A gate(32) is formed on the channel region. A first insulating film sidewall(50) is formed on the gate.

    Abstract translation: 目的：提供隧道场效应晶体管（TFET）及其制造方法，以使用自对准工艺和侧壁工艺将沟道的长度减小到小于或等于纳米级尺寸。 构成：在绝缘体上硅衬底的硅层上形成源极（14）和漏极（12），以预定间隔间隔开。 源基于金属硅化物形成。 基于n +掺杂层形成漏极。 栅极绝缘层（20）形成在沟道区域和漏极上。 在沟道区上形成栅极（32）。 第一绝缘膜侧壁（50）形成在栅极上。

    워드라인 더블 패터닝 공정방법 및 이에 의하여 구현된 낸드 플래시 메모리 어레이
    82.
    发明公开
    워드라인 더블 패터닝 공정방법 및 이에 의하여 구현된 낸드 플래시 메모리 어레이 无效
    字线双重图案处理方法和由其组成的NAND闪存存储阵列

    公开(公告)号：KR1020100111798A

    公开(公告)日：2010-10-18

    申请号：KR1020090030181

    申请日：2009-04-08

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  윤장근

    IPC: H01L21/8247 ,  H01L21/28

    CPC classification number: H01L21/28132 ,  H01L27/11524

    Abstract: PURPOSE: A method for word-line double patterning process and a NAND flash memory array fabricated by the same are provided to increase bit density by double patterning word-lines. CONSTITUTION: A dielectric layer(30) is formed on a substrate(10). A first conductive material is stacked on the dielectric layer. A first word-line(42) is formed by etching the first conductive material. An isolating oxide film is formed on the first word-line. A second conductive material is stacked on the substrate. A second word-line(44) is formed by etching the second conductive material.

    Abstract translation: 目的：提供一种用于字线双重图案化处理的方法和由其制造的NAND快闪存储器阵列，以通过双重图案化字线来增加位密度。 构成：在基板（10）上形成介电层（30）。 第一导电材料层叠在电介质层上。 通过蚀刻第一导电材料形成第一字线（42）。 在第一字线上形成隔离氧化膜。 第二导电材料层叠在基板上。 通过蚀刻第二导电材料形成第二字线（44）。

    수직 적층된 다중 비트 라인들을 갖는 노아 플래시 메모리 어레이 및 그 제조방법
    83.
    发明公开
    수직 적층된 다중 비트 라인들을 갖는 노아 플래시 메모리 어레이 및 그 제조방법 有权
    具有垂直多点的NOR闪存阵列及其制造方法

    公开(公告)号：KR1020100031319A

    公开(公告)日：2010-03-22

    申请号：KR1020080090354

    申请日：2008-09-12

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  윤장근

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/2463 ,  H01L21/265 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/76224 ,  H01L27/10891

    Abstract: PURPOSE: A NOR flash memory array including a vertical multi-bit lines and a method for manufacturing the same are provided to prevent upper and lower bit lines from being asymmetric using diffused impurity-doped layers as the bit lines. CONSTITUTION: Silicon pins(12, 14) are formed on a silicon substrate(10). Upper and lower bit lines(BL) are formed beside the silicon pins. The upper and the lower bit lines are spaced apart. Word lines(WL) which cover the silicon pins are formed to be spaced apart to the direction of bit lines. Each bit line is composed of an impurity doped layer. At least two insulation layers are formed beside the both side of the silicon pins and between word lines.

    Abstract translation: 目的：提供包括垂直多位线的NOR闪存阵列及其制造方法，以防止使用扩散杂质掺杂层作为位线的上位线和下位线不对称。 构成：硅引脚（12,14）形成在硅衬底（10）上。 在硅引脚旁边形成上下位线（BL）。 上位线和下位线间隔开。 覆盖硅引脚的字线（WL）形成为与位线的方向间隔开。 每个位线由杂质掺杂层组成。 在硅引脚的两侧和字线之间形成至少两个绝缘层。

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