公开(公告)号：KR1020060101686A

公开(公告)日：2006-09-26

申请号：KR1020050023229

申请日：2005-03-21

Applicant: 삼성전자주식회사

Inventor： 박병국 ,  고윤성 ,  우정환

IPC: H01L21/68

Abstract: 본 발명은 칩 접착 설비의 기판 공급 장치에 관한 것으로, 인쇄회로기판(PCB)이나 리드프레임(lead frame)과 같은 기판을 인덱스 레일(index rail)로 공급하는 기판 공급 장치의 설치공간을 최소화하기 위해서, 인쇄회로기판을 공급하는 매거진(magazine) 유닛에 리드프레임을 공급하는 스태커(stacker) 유닛이 결합된 칩 접착 설비의 기판 공급 장치를 제공한다.
컨베이어, 리프트, 승강기, 폭 가변 레일, 픽 앤 플레이스, 푸셔

公开(公告)号：KR102002380B1

公开(公告)日：2019-07-23

申请号：KR1020120112510

申请日：2012-10-10

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 선민철 ,  박병국

IPC: H01L29/78 ,  H01L21/336

公开(公告)号：KR101801077B1

公开(公告)日：2017-11-27

申请号：KR1020120003147

申请日：2012-01-10

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 선민철 ,  박병국

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/76889 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2409 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 제1 단결정실리콘을갖는기판상에 SiGe를갖는희생패턴을형성한다. 상기희생패턴상에제2 단결정실리콘을갖는바디를형성한다. 상기바디상에능동소자를형성한다. 상기희생패턴, 상기바디및 상기능동소자를덮는층간절연막을형성한다. 상기층간절연막을관통하여상기희생패턴을노출하는콘택홀을형성한다. 상기희생패턴을제거하여빈 공간을형성한다. 상기콘택홀 및상기빈 공간내에비정질실리콘막을형성한다. 상기비정질실리콘막을금속실리사이드막으로변환(transform)한다.

Abstract translation: 在具有第一单晶硅的衬底上形成具有SiGe的牺牲图案。 具有第二单晶硅的主体形成在牺牲图案上。 由此在身体上形成有源装置。 由此形成覆盖牺牲图案，主体和有源元件的层间绝缘膜。 通过层间绝缘膜形成接触孔以暴露牺牲图案。 牺牲图案被移除以形成空的空间。 并且在接触孔和空隙空间中形成非晶硅膜。 并将非晶硅膜转化为金属硅化物膜。

公开(公告)号：KR1020150063232A

公开(公告)日：2015-06-09

申请号：KR1020130147603

申请日：2013-11-29

Applicant: 삼성전자주식회사

Inventor： 이병준 ,  가지나미,마사토 ,  유키모리,요시아키 ,  김상윤 ,  김희재 ,  박병국 ,  석승대 ,  신재봉 ,  최병갑

IPC: H01L21/50

CPC classification number: H01L21/67259 ,  H01L21/67109 ,  H01L21/67144 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/73204 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/7598 ,  H01L2224/81127 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/83127 ,  H01L2224/83204 ,  H01L2224/8385 ,  H01L2224/92125 ,  H05K13/046 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: 반도체제조장치가제공된다. 반도체제조장치는, 제1 영역에배치된적어도하나의칩을픽업하는픽업유닛; 픽업된칩을공급받아, 제1 영역에서제2 영역에배치된회로기판상으로이동하는본딩헤드; 및제1 영역에서제2 영역으로이동하는동안, 상기회로기판상의본딩위치를검출하는광학유닛을포함한다.

Abstract translation: 提供了半导体制造装置。 根据本发明的半导体制造装置包括：拾取单元，用于拾取设置在第一区域中的至少一个芯片; 接合头以接收所拾取的芯片，以将芯片从第一区域移动到布置在第二区域中的电路板上; 以及光学单元，用于在芯片从第一区域移动到第二区域时检测电路板上的接合位置。

公开(公告)号：KR1020130078222A

公开(公告)日：2013-07-10

申请号：KR1020110147035

申请日：2011-12-30

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 선민철 ,  박병국

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: PURPOSE: A method for manufacturing a semiconductor device and a related device are provided to prevent the exposure of a substrate by forming a deep junction in a substrate. CONSTITUTION: A device isolation layer (13) is formed on a substrate. An active area (12) is defined in the device isolation layer. A gate dielectric layer (15) is formed on the active region. A gate electrode (17) is formed on the gate dielectric layer. The active region includes P-type or N type impurities.

Abstract translation: 目的：提供一种用于制造半导体器件和相关器件的方法，以通过在衬底中形成深结而防止衬底的暴露。 构成：在衬底上形成器件隔离层（13）。 活动区域（12）被定义在设备隔离层中。 在有源区上形成栅介质层（15）。 在栅极电介质层上形成栅电极（17）。 有源区包括P型或N型杂质。

公开(公告)号：KR1020130063175A

公开(公告)日：2013-06-14

申请号：KR1020110129558

申请日：2011-12-06

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 선민철 ,  박병국

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/0673 ,  H01L29/7854 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/772

Abstract: PURPOSE: A field effect transistor having a back-gate and a method for forming the same are provided to effetely restrain an off-state leakage current and to secure a semiconductor device having excellent electrical properties. CONSTITUTION: A back-bias region(37) is formed on a substrate(11). A filling isolation layer(15) covers the substrate and the back-bias region. A body is partly overlapped with the back-bias region. A drain(47) is contacted with the body. A gate electrode(25) covers the upper and the lateral surface of the body.

Abstract translation: 目的：提供具有背栅的场效应晶体管及其形成方法，以有效地抑制截止状态的漏电流并确保具有优异电性能的半导体器件。 构成：在衬底（11）上形成背偏置区（37）。 填充隔离层（15）覆盖基板和背偏置区域。 身体部分地与背偏置区域重叠。 排水口（47）与身体接触。 栅电极（25）覆盖主体的上表面和侧表面。

公开(公告)号：KR1020120049720A

公开(公告)日：2012-05-17

申请号：KR1020100111121

申请日：2010-11-09

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 권대웅 ,  박병국 ,  김창정 ,  박재철

IPC: G09G3/30

CPC classification number: G09G3/3233 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G3/30 ,  G09G3/32

Abstract: PURPOSE: A driving method of an active type display device is provided to recover threshold voltage of a thin film transistor by applying negative bias voltage to a drain electrode of a switching transistor. CONSTITUTION: A switching transistor is connected to a pixel. Negative bias voltage is applied to the switching transistor. The negative bias voltage is applied before charging each pixel. Threshold voltage of the switching transistor is recovered. The negative bias voltage is applied to a drain electrode of the switching transistor.

Abstract translation: 目的：提供一种有源型显示装置的驱动方法，通过向开关晶体管的漏极施加负偏置电压来恢复薄膜晶体管的阈值电压。 构成：开关晶体管连接到像素。 负偏置电压施加到开关晶体管。 在对每个像素充电之前施加负偏压。 恢复开关晶体管的阈值电压。 负偏压施加到开关晶体管的漏电极。

公开(公告)号：KR1020110081623A

公开(公告)日：2011-07-14

申请号：KR1020100001878

申请日：2010-01-08

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 오정훈 ,  유경창 ,  박병국 ,  오경석 ,  백인규

IPC: G11C16/00 ,  G11C16/30 ,  G11C11/21

CPC classification number: G11C13/0002 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/102 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: PURPOSE: A semiconductor devices and a method of driving the same are provided to implement high integration by preventing the interference between nonvolatile memory cells. CONSTITUTION: In a semiconductor devices and a method of driving the same, a unit cell structure(1) comprises electrode layers(M1,M2), a bipolar resistance memory material film(RM1), and a unipolar resistance memory material film(RM2) The bipolar resistance memory material film and the unipolar resistance memory material film are formed between electrode layers which are opposite to each other. The bipolar resistance memory material film and the unipolar resistance memory material film are electrically serially connected. The electrode layers include resistance memory material films which are connected to conductive lines respectively.

Abstract translation: 目的：提供半导体器件及其驱动方法，以通过防止非易失性存储单元之间的干扰来实现高集成度。 构成：在半导体器件及其驱动方法中，单元电池结构（1）包括电极层（M1，M2），双极性电阻记忆材料膜（RM1）和单极电阻存储材料膜（RM2） 双极性电阻记忆材料膜和单极电阻记忆材料膜形成在彼此相对的电极层之间。 双极性电阻记忆材料膜和单极性电阻记忆材料膜电连接。 电极层包括分别连接到导线的电阻记忆材料膜。

公开(公告)号：KR1020080051014A

公开(公告)日：2008-06-10

申请号：KR1020070095665

申请日：2007-09-20

Applicant: 삼성전자주식회사

Inventor： 박병국 ,  박일한 ,  채수두 ,  김정우 ,  한정희 ,  박찬진

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L27/2481

Abstract: An AND-type and NOR-type flash memory arrays, a manufacturing method thereof and an operating method thereof are provided to form plural same silicon pins having certain width and height on an upper portion of a substrate. A local bit line(LBL1) is connected to bit lines(BL1,BL2,BLn) via a first select transistor(ST11). Memory cells(M11 to Mm1) are connected in parallel to the local bit line and the local source line. A local source line(LSL1) is commonly connected to a source of the respective memory cells, and a common source line(CSL) is connected to the local source line via a second select transistor(ST21). A drain select line(DSL) and a source select line(SSL) are electrically connected to a gate of the first select transistor and a gate of the second select transistor. Plural word lines(WL1 to WLm) are connected to a gate of each memory cell. The local bit line and the local source line have a first doped layer and a second doped layer which are vertically spaced apart from silicon pins.

Abstract translation: 提供AND型和NOR型闪速存储器阵列，其制造方法和操作方法，以在衬底的上部上形成具有一定宽度和高度的多个相同的硅销。 局部位线（LBL1）经由第一选择晶体管（ST11）连接到位线（BL1，BL2，BLn）。 存储单元（M11〜Mm1）与本地位线和本地源极线并联连接。 本地源极线（LSL1）通常连接到各个存储单元的源极，并且公共源极线（CSL）经由第二选择晶体管连接到本地源极线（ST21）。 漏极选择线（DSL）和源选择线（SSL）电连接到第一选择晶体管的栅极和第二选择晶体管的栅极。 多个字线（WL1至WLm）连接到每个存储单元的栅极。 局部位线和局部源极线具有与硅引脚垂直间隔开的第一掺杂层和第二掺杂层。

公开(公告)号：KR1020040085663A

公开(公告)日：2004-10-08

申请号：KR1020030020444

申请日：2003-04-01

Applicant: 삼성전자주식회사

Inventor： 이용규 ,  한정욱 ,  강성택 ,  이종덕 ,  박병국

IPC: H01L27/115

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

Abstract: PURPOSE: A method for fabricating a twin-ONO type SONOS memory device using a reverse self-aligning process is provided to control distribution of charges in an ONO dielectric layer by improving a SONOS memory fabrication method. CONSTITUTION: An ONO dielectric layer(500) is formed on a substrate. A buffer layer having a trench(601) is formed on the ONO dielectric layer. The ONO dielectric layer is partially exposed by the trench. The first conductive spacer(700) is formed on an inner wall of the trench. The ONO dielectric layer is divided into two parts by removing selectively the exposed part of the ONO dielectric layer. A gate dielectric layer(800) is formed on the substrate. The second conductive layer(900) is formed on the gate dielectric layer in order to fill up a gap between both sidewalls of the trench. The buffer layer is removed by using the first conductive spacer as an etch mask. The ONO dielectric layer is patterned by removing selectively the exposed part of the ONO dielectric layer.

Abstract translation: 目的：提供一种使用反向自对准工艺制造双ONO型SONOS存储器件的方法，以通过改进SONOS存储器制造方法来控制ONO电介质层中的电荷分布。 构成：在基板上形成ONO电介质层（500）。 在ONO电介质层上形成具有沟槽（601）的缓冲层。 ONO电介质层由沟槽部分露出。 第一导电间隔物（700）形成在沟槽的内壁上。 通过选择性地去除ONO介电层的暴露部分，将ONO介电层分成两部分。 在基板上形成栅介质层（800）。 为了填充沟槽的两个侧壁之间的间隙，在栅极介电层上形成第二导电层（900）。 通过使用第一导电间隔物作为蚀刻掩模去除缓冲层。 通过选择性地去除ONO电介质层的暴露部分来对ONO电介质层进行构图。